Design Layout Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions! In this position, you will collaborate with Micron’s various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will own physical implementation and top-level integration of large digital designs in our NAND products. Drive blocks and full-chip partitions through synthesis handoff, floorplan, place-and-route, and timing/DRC/LVS closure. Perform hierarchical design planning and top-level assembly. Responsibilities will include, but are not limited to: Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions Leading all aspects of and managing the layout process including floor-planning, placement, and routing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The qualifications and skills for this position include, but are not limited to: Bachelor’s or master’s degree in Electrical Engineering or Computer Engineering with 7+ years of proven experience in Test Engineering role. Excellent programming skills for writing and debugging ATE test programs and test-related hardware development. Proficiency with Advantest V93K ATE platforms and/or other logic device ATE testers is preferred. Proficiency in programming with C/C++ and/or JAVA is required. Solid understanding of testing for CMOS SoCs. Prefer candidates with exceptional digital, analog, and MXS test programming and debug experience. Familiar with testing IP blocks such as PLL, efuse, DDR. Expertise in test strategy development, test plan definition, DFT pattern implementation (ATPG SCAN, TDF, MemBIST and repair, BSACAN, JTAG/IEEE1500, and Functional Patterns). Expertise in ATE architecture and test hardware design and debugging, schematic capture, and PCB layout. ATE test vector conversion tools like VTRAN and proficiency in debugging issues during development or high volume production. Knowledge of semiconductor manufacturing process. Knowledge of accurate and effective use of lab test equipment (i.e., oscilloscope, logic analyzer, etc.). Experience with data analysis software in support of c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Power Delivery Network (PDN) Engineer , you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next-generation HBM products. You will work closely with architecture, design, physical design, packaging, and product engineering teams to ensure robust, efficient, and manufacturable power delivery solutions that meet aggressive performance, power integrity, and reliability targets. This is a hands-on technical role focused on PDN design, EM/IR analysis, and cross-domain optimization across technology, design, and layout. Key Responsibilities Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes. Perform EM/IR analysis and optimization using industry-standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads. Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation. Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks. Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution. Develop and validate power models, including activity-based current profiles and transient analysis for realistic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years or MSEE with 5+ years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years, or MSEE with 5+ years of releva

P-1093 At Databricks, we are passionate about enabling data teams to solve the world’s toughest problems — from making the next mode of transportation a reality to accelerating the development of medical breakthroughs. We do this by building and running the world’s best data and AI infrastructure platform so our customers can use deep data insights to improve their business. Founded by engineers — and customer obsessed — we leap at every opportunity to tackle technical challenges, from designing next-gen UI/UX for interfacing with data to scaling our services and infrastructure across millions of virtual machines. And we're only getting started. The ManagedTables team at Databricks is responsible for the DataIntelligence initiatives that underpin the Unity Catalog ManagedTables offering. This encompasses products such as Predictive Optimization, Liquid Clustering, and control plane services facilitating Unity Catalog and Iceberg Rest Catalog API-based access to ManagedTables. The team is accountable for optimizing exabytes of data and saving millions of dollars annually for our customers through the Data Intelligence offerings. As part of this team, you will be working on realizing enterprise grade autonomous analytical datasystems - that ensure the best performance out-of-the-box. You will design and implement these next gen systems that leapfrog state-of-the-art: Storage lifecycle and additional background optimizations for a knob-free experience via Predictive Optimization Efficient storage structures and innovations to power storage layout solutions for the ML world Influence the Data format and Catalog interface unification efforts and enable strong ecosystem interoperability for ManagedTables The Impact you will have: Solve real business needs at large scale by applying your software engineering experience and by driving strong collaboration with Product partners Deliver a highly scalable, available, and inter-operable architecture for Managed Tables. Lo

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role Summary As part of the Access team, you’ll work in a fast-paced, innovation-driven environment. We believe in challenging assumptions, breaking limitations, and creating elegant solutions to complex problems. We’re not just building products—we’re building what’s next. Ready to bring bold ideas to life? Join us and help redefine how the world connects. Responsibilities As an EE Engineer on the Access team, you will be responsible for the electrical design of consumer electronic products, such as door access readers/HUBs, wireless sensors, lighting controllers, and smart locks. We are looking for candidates who thrive in a fast-paced, start-up-like environment. In this role, you will own end-to-end EE hardware development, from system architecture and circuit design to board design, validation, and production readiness. Success in this role requires strong ownership, attention to detail, and a high standard of accountability. Own product architecture definition, electrical design, and system integration from concept to production. Lead and review PCB layout and electrical simulation activities. Plan and execute design validation, including functional verification, signal characterization, power analysis, and system coexistence testing. Troubleshoot and resolve hardware issues throughout development and prototype builds

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. We have an opening for Yield Analysis Engineer for NAND Technology Department in Singapore. We are looking for candidate that is passionate to innovate in data analytics, and curious to ask "what, how and why"? In this role you will be responsible for providing key feedback and direction on yield improvement activity for NAND memory technology! This role requires a high degree of collaboration across virtually all company functions, up to and including the Executive level. As Yield Analysis Engineer , you will be responsible for developing innovative NAND product technologies, define, and execute various effective actions to enable solutions to improve yield, quality, reliability, and hit key milestones & achieve the required performance within committed timelines. Your responsibilities will include, but are not limited to, the following: Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification Interact with process area, process integration, yield, failure analysis, product engineering, design, and layout teams to drive clear definition of yield, cell, CMOS,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has advanced the world’s most innovative memory and semiconductor technologies. As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next‑generation high‑bandwidth memory products. You will evaluate block‑level and full‑chip functionality, solve complex challenges in building, and collaborate with a distributed team to deliver highly reliable, industry‑leading HBM solutions. This role provides the opportunity to contribute to groundbreaking DRAM design, TSV‑based 3D integration, and high‑speed mixed‑signal architectures supporting Machine Learning and AI applications. Responsibilities Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Photolithography Process Development Engineer in Micron's R&D/Technology Development group, you will be responsible for process module development for memory devices, in addition to other photolithography and process integration related activities. In this position, you will work with Micron engineers, technology partners and vendors to develop unit processes that meet device requirements for next-generation semiconductors, integrate processes as part of multi-functional teams and ultimately provide technology transfers to Micron’s worldwide manufacturing network. Additionally, you will address process issues with pilot line manufacturing and work on continuous improvements for manufacturability. Advanced process development tasks will include: Performing material evaluations; reticle, layout and OPC development; process window analysis; overlay optimization. Responsibilities include, but are not limited to: Document procedures, transfer developed processes, and communicate results with senior management team and manufacturing partners Work jointly with equipment vendors to improve equipment design, test new equipment, and drive pro

Who We Are Verkada is transforming how organizations protect their people and places with an integrated, privacy-sensitive AI-powered platform that includes solutions for video security, access control, air quality sensors, alarms, intercoms, and visitor management. We’ve got serious momentum in the market: more than 30,000 customers (including 100+ of the Fortune 500), a $5.8B valuation , more than $1 billion in annualized bookings, and backing from CapitalG, Sequoia Capital, General Catalyst, Felicis Ventures, Next47 and more. Physical AI is one of the most consequential technology shifts of our time, and Verkada is at the center of it. You can look at all kinds of communities to see our platform’s impact in the world. It's the retailer that uses our agentic AI to deter theft before it happens. The warehouse that uses AI-powered alerts to make sure its team is protected on the floor with proper PPE. The school that’s alerted to a threat in real-time and triggers a lockdown in seconds, not minutes. We’re rapidly scaling this impact: today, more than 2 million Verkada devices are deployed across 170+ countries. About the Role As a Hardware Engineering Intern at Verkada, you’ll contribute to the design and development of new cameras, access control systems, sensors, and other enterprise IoT products. Verkada’s Hardware Engineers own all aspects of the electrical design from prototype through to mass production. You’ll make a big impact — your designs will be a part of future products that Verkada ships. This is a full-time internship, in-person role based in our San Mateo, CA office. What You'll Do Partner with experienced engineers to design, debug, and validate our hardware products. Design and execute experiments to test new circuit concepts. Schematic capture and layout for systems and/or test boards. Learn to work with our manufacturing partners to drive ongoing improvements to efficiency. What You Bring Pursuing a degree in Electrical Engineering or

Who We Are Verkada is transforming how organizations protect their people and places with an integrated, privacy-sensitive AI-powered platform that includes solutions for video security, access control, air quality sensors, alarms, intercoms, and visitor management. We’ve got serious momentum in the market: more than 30,000 customers (including 100+ of the Fortune 500), a $5.8B valuation , more than $1 billion in annualized bookings, and backing from CapitalG, Sequoia Capital, General Catalyst, Felicis Ventures, Next47 and more. Physical AI is one of the most consequential technology shifts of our time, and Verkada is at the center of it. You can look at all kinds of communities to see our platform’s impact in the world. It's the retailer that uses our agentic AI to deter theft before it happens. The warehouse that uses AI-powered alerts to make sure its team is protected on the floor with proper PPE. The school that’s alerted to a threat in real-time and triggers a lockdown in seconds, not minutes. We’re rapidly scaling this impact: today, more than 2 million Verkada devices are deployed across 170+ countries. About this Role As a Hardware Engineer on our hardware team, you will lead the design and development of Verkada’s newest products. Verkada’s Hardware Engineers own all electrical engineering design and validation aspects, working directly with our JDM partners to ship cutting-edge products. This is a full-time, in-person role based in our San Mateo, CA office. What You'll Do Lead electrical engineering for new products from initial proof of concept through to mass production. Collaborate with US and an international team of hardware engineers, mechanical engineers, industrial designers, software engineers and product managers to develop new products. Own component selection, schematic and layout development based on the architecture you have created. Own and maintain Hardware Requirements Document, ensuring it

Our Global Structure Deliveroo is now part of DoorDash, bringing together teams with even greater reach, scale, and ambition. Depending on your role, you may collaborate with teammates, systems, and leaders across DoorDash and Wolt. Together, we’re unlocking new possibilities as one global team. About the role We are looking for an Engineering Manager to lead Codeless, our internal Server-Driven UI (SDUI) platform team. In this role, you will lead a cross-functional team bridging mobile/web frontend engineering and core platform backend systems. While this role is deeply rooted in modern UI architecture, its mission goes beyond standard UI development: Codeless empowers product teams across the organization to ship dynamic, native UI experiences dynamically from the backend—eliminating app store release bottlenecks, dramatically accelerating feature iteration, and establishing a unified UI schema across iOS, Android, and Web. What you’ll be doing This is a role with broad impact, from hands-on technical guidance to championing web and mobile accessibility across the company. We're looking for a leader who excels at fostering collaboration and can confidently guide a concept from initial idea to robust implementation. Day-to-day in this role you’ll: Team Leadership & Strategy: Build, mentor, and scale an engineering team responsible for our core Server-Driven UI platform ("Codeless"). Foster an inclusive, high-ownership engineering culture. Platform Architecture & Evolution: Oversee the design and evolution of dynamic layout engines, declarative UI schemas, and client rendering frameworks across iOS, Android, and Web. Developer Velocity & Platform Adoption: Partner with product feature teams to drive internal adoption of Codeless. Ensure the platform provides exceptional Developer Experience, clear tooling, robust design system integration, and seamless debugging workflows. Technical Execution & Quality: Set high technical standards for platform perfo

Celonis is the trusted platform to industrialize Enterprise AI. At our core is the Celonis Context Model — which combines process data, business knowledge, and intelligence into a living digital twin of the enterprise that AI can actually understand, turning AI's operational blind spots into operational clarity. World's leading companies trust Celonis and its global ecosystem of partners to make their AI agents, people, systems, and processes work together, achieving transformational outcomes. We believe there's a massive opportunity to unlock global productivity and sustainability by giving AI the context to understand how every business process really works. Join our mission to make processes work for people, companies, and the planet. The Team Prisma is a newly formed team building the Modeling Library that powers Celonis' Process Modeling Experiences. This library is the foundation for how users create, edit, and visualize process models across the platform. The team works closely with Product, UX, and other engineering teams to turn complex modeling and graph problems into fast, intuitive interactions for our customers. The Role As a Senior Software Engineer on Prisma, you'll help build and grow the Modeling library from the ground up. You'll work on the graph rendering, layout, and interaction logic that lets users model business processes clearly and efficiently, even with large and complex data sets. We're looking for engineers who already use AI coding tools daily and know how to apply them to solve real engineering problems fast, not as a novelty, but as part of how they build production-quality software. The work you'll do Design and build the Modeling library's core components using TypeScript, Angular, and HTML5. Solve complex visualization problems such as fast interactions, dynamic graph layouts, and graph interactions, to Celonis' quality bar Use AI coding tools daily to speed up development and problem-solving on graph layout, rendering, and in

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is seeking an experienced and highly motivated individual to join our team as a Senior Advanced CMOS Device & Process Integration Engineer. The successful candidate will combine strong engineering judgment with AI-assisted analytics ( Claud Assist, Code Assist, etc. ), coding, modeling, and knowledge-management tools to accelerate technology development and improve the quality and efficiency of technical decision-making. AI is expected to enhance, rather than replace, the engineer’s technical ownership, device expertise, and accountability. This position provides an opportunity to make significant technical contributions to current and future CMOS technologies for advanced memory products. As a Senior Advanced CMOS Device & Process Integration Engineer, you will own key device or process integration workstreams within advanced CMOS technology development. You will work closely with Process Engineering, Circuit Design, Layout, Product Engineering, Reliability, Manufacturing, Yield Enhancement, and Modeling/TCAD teams to define technical requirements, plan silicon experiments, resolve complex device issues, and transfer robust technologies into high-volume manufacturing. You will be expected to independently identify technical risks, develop data-driven solutions, and influence cross-functional engineering decisions. Responsibilities inc