Design Layout Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are hiring a Layout Engineer for Micron Technology’s HBM Team in Hyderabad, India. In this role, you will contribute to advanced applications including artificial intelligence and high-performance computing solutions with High Bandwidth Memory. You will coordinate with peer groups across Micron's worldwide locations on multiple projects, providing an exceptional chance for career development! Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership qualities in area/time estimation, scheduling, and execution to meet project schedule/milestones in multiple project environments. • Ability to guide Peer team-members in their execution of Sub block-level layouts & review critical items. • Effectively communicating with Local engineering teams to assure the success of layout project

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Develops and prepares multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. May check design layouts and detailed drawings. Position overview: As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will provide detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers, verify data integrity, and take the lead in major block developments. You’ll be expected to communicate effectively with other functional groups across global sites, e.g. TD, design, verification, and CAD. We’re seeking a self-starter who can learn rapidly and adapt quickly to changing priorities. Responsibilities: Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution Contribute to group management and technical innovation Assign resources, schedule tasks, provide direction, and deliver quality-controlled results Contribute to projects in a globally distributed design/layout environment</span

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Layout Designer, you will develop and prepare multi-dimensional layouts. You will provide detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers, verify data integrity, and take the lead in major block developments. You’ll be encouraged to communicate optimally with other functional groups across global sites, e.g. TD, design, verification, and CAD. We’re seeking a self-starter who can learn rapidly and adapt quickly to changing priorities. What’s Encouraged Daily: Coordinate and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution Contribute to group management and technical innovation Time management skills and prioritizing tasks and deliver quality-controlled results. Contribute to projects in a globally distributed design/layout environment Contribute to the improvement of layout efficiency through the development of automation and new methodologies; plan, and deliver major blocks and product revisions. Minimum qualifications: AS in Electronics, Electrical Engineering, or a related field plus 5&#43; years of direct experience in semiconductor layout design Deep solid understanding of EDA tools (i.e. Cadence Virtuoso, Synopsys, Calibre) Demonstrate a strong ability to debug problems through root-cause analysis, find effective and efficient solutions, and collaborate wit

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities: - Mainly focus for system schematic review and mechanical stacking review with mechanical engineers and PCB layout review with layout engineers. - Work with RF engineers to figure out performance issues of radios. - Review design derating and suggest design update due to DFM (design for manufacturing), DFA(design for assembly) and DFC (Design For Cost.) - Schematic and BOM maintain and review. - Write test plans for testing coverage, executes tests, and documents test results for projects. - Report projects’ status and issue tracking to internal. - Teardown and review new products in the market. Qualifications: - BS or MS in EE engineering. - Junior/New grads are welcome. - Leadership in a project. - Good working knowledge of system level architecture and RF fundamentals. - Basic knowledge of EE lab equipment including: oscilloscopes, multimeters, power supplies, etc. - Good understanding of RF metrics. - Proficiency on PCB and Schematic tools such as pads, allegro, orcad etc..

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities (What he/she will do after join UI): - 5~8 years’ work experience as a Key EE designer for Mobile, Tablet or AP products. - Mainly focus for system schematic review and mechanical stacking review with mechanical engineers and PCB layout review with layout engineers. - Work with RF engineers to figure out performance issues of radios and work with SI and DQA engineers to qualify features and make sure product quality is ready to move further. - Review design derating and suggest design update due to DFM (design for manufacturing), DFA(design for assembly) and DFC (Design For Cost). - Schematic and BOM maintenance and review. - Write test plans for testing coverage, execute tests, and document test results for projects. - Report projects’ status and issue tracking to internal. - Teardown and review new products in the market. Minimum Qualifications (MUST-haves) : - Have the MP experience with Mobile, Tablet or AP products. - Familiarity with high-speed signal design. - Proficiency on using OrCad Capture CIS, Power PCB viewer and Allegro viewer - Knowledge of electronic components (Ex. R/L/C/Diode/MOS/BJT/Logic ICs/Sensors) - Strong knowledge of ESD, EMI and Surge. - Debug skills with the basic operation with oscilloscopes, Logical Analyzers. - Strong knowledge to support the thermal solution. Preferred Quali

Technical Program Manager III itD is seeking a Technical Program Manager III to drive hardware program execution for next-generation AR wearable devices. This role will play a critical part in managing PCB development and electrical component integration, ensuring seamless collaboration between electrical engineering, layout, and manufacturing teams. The ideal candidate will bring deep experience in hardware engineering or program management and a proven track record of delivering complex PCB and wearable device programs from design through production. Location: Onsite – Sunnyvale, CA Duration: 12 Months (potential for extension / FTE conversion) Pay Rate: $75 - $80 per hour, depending on experience We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities Lead end-to-end program management of PCB development, including flex circuits and multi-layer boards (MLBs) from design through production Drive design release processes, ensuring alignment across electrical engineering, layout, and cross-functional teams Manage SMT (Surface Mount Technology) and FATP (Final Assembly, Test, and Pack) builds, optimizing for schedule, quality, and yield Collaborate closely with electrical and layout engineers to develop and refine circuit designs for compact wearable devices Track program schedules, dependencies, and risks, proactively driving mitigation strategies Coordinate with APAC-based teams and vendors, including participation in early morning or evening meetings Ensure successful integration of small electrical components into advanced AR wearable form factors Provide strong program leadership, driving ownership, clarity, and execution across stakeholders Internal Responsibilities Attend regular internal practice community meetings Collaborate with your itD practice team on industry thought leadership Complete client case

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design and implement physical layouts for advanced digital, analog, and mixed-signal circuits used in the development of memory products. Responsible for translating schematics into high quality, manufacturable layouts that meet process rules, performance targets, and schedule commitments, while collaborating closely with cross functional engineering teams. Create physical layouts of transistors, resistors, capacitors, and interconnect structures for digital, analog, and mixed-signal circuits. Perform block-level floor planning, including layout area estimation and optimization. Develop IC top-level floorplans and provide accurate total die area estimates. Execute routing, power bus design, and creation of robust PDN (Power Domain Network) solutions to ensure optimal electrical performance, reliability, and scalability. Ensure layouts comply with foundry process design rules and verify layout-versus-schematic (LVS) and design rule checks (DRC). Apply recommended layout, verification techniques, tools, and design flows to deliver high-quality designs on schedule. Work closely with analog/mixed-signal and digital design engineers to ensure proper layout implementation, including critical matching and symmetry requirements. Collaborate with Design Engineering, Product Engineering, Process Integration, Probe, and Assembly teams to proactively optimize designs for manufacturability, cost, quality, reliability, and time-to-market. Create and maintain layout-related documentation and actively participate in layout and design reviews. Support continuous improvement of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Lead Principal Engineer, Layout Design at Micron, you will be at the forefront of developing groundbreaking memory solutions! This role is an outstanding opportunity to lead the physical implementation of modern DRAM and mixed-signal circuits, turning schematics and specifications into flawless, manufacturable layouts. You will collaborate with a world-class team of Circuit Designers, Verification Engineers, CAD/Methodology experts, Process Integrators, Product Engineers, Test/Probe specialists, Assembly professionals, and Marketing strategists. Together, we will drive cost, quality, reliability, time-to-market, and customer happiness through outstanding layout and build. Key Responsibilities Lead the layout build and physical realization of new memory products. Interpret device and circuit specifications to implement custom layout solutions meeting PPA (power, performance, area) and reliability targets. Develop hierarchical layouts for analog, digital, and memory-array-related circuitry using industry-standard EDA tools. Build block and top-level floorplans optimizing placement, routing resources, signal integrity, power delivery, and manufacturability. Optimize layout for critical metrics such as die size/area efficiency, matching, coupling/noise, and timing. Produce layout collateral and documentation for cross-team integration. Physical Verification and Tapeout Signoff Run and debug physical verification flows and ensure closure using indust

Staff Engineer, Scribe Layout Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is seeking a highly experienced Staff Engineer for Design Enablement and Layout in Advanced Packaging Technology Development. This role involves coordinating cross-functional engineering teams across geographies to develop and optimize design rules, requirements, design, and layout from early development through manufacturing! Job Description: Responsibilities will include, but are not limited to: Develop and refine Design Rules, Requirements, and Test Structures for advanced packaging. Create layout and DBR test vehicle and product designs to support technology development. Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations. Analyze large datasets to extract meaningful insights and drive data-driven decision-making. Leverage of artificial intelligence to reduce development time. Manage structure evaluation to support development and quantify process margins. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams. Minimum Qualifications: BS/MS/PhD in Electrical Engineering, Microelectronics, Physics, or related field. 5&#43; years of experience in semiconductor industry in areas such as Process Integration, Yiel

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is seeking an engineer for Design Enablement and Layout in Advanced Packaging Technology Development. This role involves coordinating cross-functional engineering teams across geographies to develop and optimize design rules, requirements, design, and layout from early development through manufacturing! Job Description Key Responsibilities: Develop and refine Design Rules, Requirements, and Test Structures for advanced packaging. Create layout and DBR test vehicle and product designs to support technology development. Ensure robust Design Rule Checks (DRC) and appropriate responses to deviations. Analyze large datasets to extract meaningful insights and drive data-driven decision-making. Leverage of artificial intelligence to reduce development time. Manage structure evaluation to support development and quantify process margins. Strategically partner with teams to resolve process issues related to layout and prioritize solutions. Document and communicate complex problem resolutions and drive cross-node design rule alignment. Maintain effective communication across Process Integration, Product Engineering, Design, and Advanced Mask teams. Minimum Qualifications: BS/MS/PhD in Electrical Engineering, Microelectronics, Physics, or related field. 2&#43; years of experience in semiconductor industry in areas such as Process Integration, Yield Enhancement, Product Engineering, Design, Test Structure Development

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead front-end semiconductor fab design and process tool planning activities for new fab construction, expansion, and remodeling projects. Develop and maintain cleanroom layout strategies that optimize manufacturing capacity, operational efficiency, equipment accessibility, and future scalability. Evaluate and define tool siting plans, process area configurations, aisle strategies, and support space requirements to enable manufacturing objectives. Partner with Process Engineering teams to translate technology roadmaps and capacity requirements into executable facility and layout solutions. Collaborate with Facilities, Utilities, Construction, and AMHS teams to ensure successful integration of manufacturing equipment, infrastructure systems, and material handling networks. Drive footprint optimization, cleanroom utilization improvement, and layout scenario analysis through data-driven decision-making. Coordinate design reviews and alignment discussions across multiple stakeholder groups to ensure project objectives, timelines, and requirements are met. Support fab readiness activities, including field verification, design validation, issue resolution, change management, and risk mitigation. Ensure compliance with safety, quality, environmental, and corporate standards throughout all design and implementation ph

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams. Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis. Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures. Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams. Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams. Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs. Qualifications: Master’s degree i

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Lead end-to-end layout execution of analog, mixed-signal, custom digital blocks and full-chip integration for HBM products. Own full-chip technical decisions covering analog, digital, memory, ESD, EM/IR and ensure optimal performance, power, and area (PPA). Technical Expertise : Hands-on experience in layout design of critical Memory /Analog and mixed-signal blocks such as: Array Layout, Decoder, Control logic , IOs , PLLs , ADCs, DACs, LDOs, Bandgaps, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers. Drive project planning and execution , including area/time estimation, scheduling, task delegation, and milestone tracking across multiple concurrent programs. Ensure timely delivery with quality , responsible for block-level and full-chip layouts meeting schedule commitments and quality expectations. Perform and oversee layout verification activities including LVS, DRC, Antenna checks, and ensure closure with proper documentation and audits. Lead and mentor the layout team , guiding junior engineers on sub-block execution, conducting design reviews, and enabling capability development. Drive innovation and productivity improvements , including adoption of AI/automation to reduce layout effort, improve turnaround time, and enhance quality. <li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Design Engineer, you will build the future of memory by architecting and delivering high‑performance DRAM circuit compositions for advanced technology nodes. In this highly visible technical leadership role, you’ll develop innovation across building, layout, verification, and silicon validation. You will collaborate closely with multi-functional teams to deliver scalable, manufacturable solutions for next-generation memory products. Your work will directly influence performance, power, reliability, and time‑to‑market for Micron’s groundbreaking memory technologies. Responsibilities Design and optimize DRAM circuits spanning digital, analog, and memory core subsystems to meet aggressive power, performance, and reliability targets Develop and refine floorplans, routing strategies, power delivery networks, sense margins, timings, and die‑size tradeoffs Perform advanced circuit simulations using FINESIM, HSPICE, and VERILOG, analyzing speed, power, noise, and long‑term reliability Model parasitics, verify power and signal integrity, and support validation, reticle experiments, and tape‑out revisions Drive simulation‑to‑silicon correlation, identify gaps, and recommend schematic and layout improvements Lead technical reviews, documentation, and best‑practice standardization across design and layout teams Coordinate and manage layout and build resources, tracking breakthroughs and resolving critical path issues S