Design Verification Engineer Intern Jobs

Principal Embedded Firmware and Software Engineer Description - We are seeking a Principal Embedded Firmware & Software Engineer to lead the design, development, and debugging of embedded software and firmware for computer systems. In this role, you will combine deep, hands-on engineering expertise with system-level technical leadership to ensure seamless integration between software and hardware components, delivering reliable and efficient system performance. You will collaborate closely with cross-functional teams including hardware engineers, software developers, QA, and product managers to bring high-quality products to market. Responsibilities Provide technical leadership for the architecture, development, security, integration, debugging, validation, and deployment of embedded firmware and software including BIOS/UEFI, EFI applications and drivers, embedded controllers, and RTOS-based systems. Analyze hardware and system architectures to define firmware requirements, dependencies, interfaces, integration strategies, and validation approaches. Troubleshoot and resolve firmware issues by designing and implementing enhancements, updates, and programming changes across firmware subsystems. Define and drive firmware integration, verification, and validation strategies, including automated testing, regression testing, and continuous integration . Develop and improve engineering tools and automation using Python and other appropriate technologies for development, debugging, testing, analysis, and validation. Advance CI/CD and DevSecOps practices for embedded development to improve engineering velocity, quality, traceability, and release confidence. Evaluate and apply AI-assisted software development and engineering tools where they can improve developer productivity,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview At the Munich Development Center, we develop high-performance memory solutions for the graphics and AI markets. As part of the DRAM Design Engineering Group (DDEG), we collaborate closely with Micron’s global development and manufacturing teams. Our mission is to push the boundaries of memory technology through innovation, precision, and partnership. Role Overview We are looking for a motivated and curious working student or Master’s thesis candidate to join our DRAM design team. This is an outstanding opportunity to gain hands-on experience in integrated circuit (IC) design while working alongside expert engineers in a collaborative, startup-like environment. You will contribute to real-world projects and receive mentorship to support your academic and professional growth. Responsibilities Support the design and simulation of analog or digital circuit blocks under guidance Assist in developing schematics at the transistor level or RTL Participate in functional verification and layout reviews Contribute to testbench development and simulation setup Document design processes and results for internal use or academic reporting Collaborate with cross-functional teams to understand the full memory design flow Leverage generative AI tools to complete tasks in effective manner Optionally: define and complete a master’s thesis project aligned with team goals Required Qualifications Enrolled in a Bachelor’s or Master’s program in Ele

About Us SharkNinja is a global product design and technology company, with a diversified portfolio of 5-star rated lifestyle solutions that positively impact people’s lives in homes around the world. Powered by two trusted, global brands, Shark and Ninja , the company has a proven track record of bringing disruptive innovation to market and developing one consumer product after another has allowed SharkNinja to enter multiple product categories, driving significant growth and market share gains. Headquartered in Needham, Massachusetts with more than 4,100 associates, the company’s products are sold at key retailers, online and offline, and through distributors around the world. AI at SharkNinja At SharkNinja, we’re building an AI-native culture. We’re not waiting for the future; we’re creating it. Our people are expected to experiment boldly, adopt new tools, and continuously raise what’s possible to create meaningful impact for our consumers. If you believe the best way to do your job hasn’t been invented yet, you’ll fit right in. About the Role: This role will focus on embedded firmware design and product development lifecycle for our ambitious product roadmap. The successful candidate will have experience in embedded firmware design, including 8-bit, 16-bit and 32-bit microcontrollers. Preferably in home appliance products or similar and would be familiar with all product development aspects such as best practice coding standards, heating control, motor control, sensor, inter-processor communications such as UART, I2C, SPI, WIFI and firmware/code verification systems. The successful candidate would have experience using analysis/measurement tools such as oscilloscopes, data loggers, DVM’s to debug embedded systems. This is where your SharkNinja journey begins. You’re an explorer—not a tour guide—driven by curiosity, fueled by taking chances, and unwilling to fly under the radar. Here, bold m

End-to-End Space Systems Engineer (Experienced or Lead) Company: The Boeing Company Boeing Defense, Space & Security (BDS), Space Mission Systems (SMS) Division, seeks an End-to-End Space Systems Engineer (Experienced or Lead) (Level 3 or 4) to join our team in El Segundo, California. Our team works with Commercial, Government, and Proprietary Customers in the development and deployment of next-generation technologies and systems in Space. The candidate will demonstrate the ability to provide high impact, creative solutions to complex technical problems, the ability to work as part of a large team, and the ability to provide critical support and independent review of the work of teammates. Position Responsibilities: Manage Space Segment External Interfaces, including development of Interface Control Documents ( ICD) as required by contract Perform system requirements and verification planning and execution Responsible for the maintaining the requirements trace and Verification Cross-Reference Matrix (VCRM) for system level requirements Develop and Model Space Segment Intersegment CONOPS Develop and maintain System Design Documents (SDDs) Utilize Model Based Systems Engineering processes and tools to develop and maintain the System Architecture Model Perform system trade studies and System level analyses Develop Intersegment Test Plans, including requirements for demonstrations and test beds Support Execution of System Operational test and evaluation activities Responsible for system level requirements verification and selloff Must be able travel locally

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . We are looking for a Staff Machine Learning Engineer to lead the technical vision for our Ads Conversion Core Modeling team, building the state-of-the-art systems that power our global marketplace. What you’ll do: Lead the technical direction and development of state-of-the-art applied ML projects for ads conversion. Design and build large-scale DNN models to improve user action prediction with low latency. Mine text, visual, and user signals to better understand intention and infer interests from online activity. Use AI to accelerate analysis and iteration, while applying judgment and verification to ensure correctness and quality. Automate repeatable tasks such as documentation, reporting, and QA checks to speed up the development lifecycle. Coach and mentor engineers whi

Experienced LO Propulsion Integration Engineer Company: The Boeing Company Come join a winning team and support the development of Boeing’s Next Generation Air Dominance (NGAD) platforms. Boeing Phantom Works is seeking an experienced Low Observable (LO) Propulsion Integration Engineer to lead LO integration of propulsion systems for advanced stealth aircraft programs. The ideal candidate will possess deep technical expertise in propulsion integration, LO design principles, and systems engineering, and will work across multidisciplinary teams to ensure propulsion system performance while maintaining stringent signature, thermal, and structural requirements. Position Responsibilities: LO propulsion integration activities for advanced platforms across concept, design, test, and qualification phases Develop and validate propulsion system LO architectures that meet performance, LO signature, and thermal management requirements Conduct trade studies, signature modeling, and sensitivity analyses for inlet, nozzle, and exhaust treatments Interface with aerodynamicists, structures, materials, thermal management, and signature engineering teams to ensure cohesive design solutions Define requirements, perform risk assessments, and establish verification/validation plans for propulsion integration items Support hardware design reviews (PDR/CDR), test planning, and ground/flight test execution to verify LO and propulsion performance Mentor junior engineers and provide technical leadership within the LO discipline Produce and review technical documentation, specifications, and interface control documents (ICDs) Basic Qualifications (Required Skills and Experience): Bachelor of

Software Engineer | Vehicle Management Systems (Associate or Experienced) Company: The Boeing Company Boeing Defense, Space & Security (BDS) has an exciting opportunity for a Software Engineer - Vehicle Management Systems to join our Experimental Systems Group (ESG) Flight Software (FSW) team in Seal Beach, California. This position will focus on supporting the Boeing Defense, Space & Security (BDS) Software Engineering organization. Our teams are currently hiring for a broad range of experience levels including; Associate and Experienced Software Engineers. This role is ideal for software engineers who enjoy working close to flight hardware and mission operations, care deeply about safety, reliability, and performance, and want to grow into a domain expert in Vehicle Management Systems (VMS) for advanced aerospace and autonomy platforms. You will collaborate with systems, flight software, and integration/test teams to translate requirements and interface control documents (ICDs) into robust architectures and executable verification strategies. You will build simulation- and hardware-in-the-loop environments, author test plans and procedures, and develop automated pipelines that validate requirements, interfaces, and performance across integration, lab, and operational settings. You will write unit/integration/system tests; contribute to CI/CD pipelines, code reviews, and documentation; and deliver concise, actionable test reports for stakeholders. Position Responsibilities: Collaborates cross-functionally to define, review, and refine vehicle management software requirements, specifications, and system-level design inputs Develops and integrate vehicle management softw

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Post-Silicon Validation Engineer to drive bring-up, validation, and debug of RISC-V–based SoCs. This role sits at the intersection of silicon, firmware, and system software, and requires hands-on lab experience and understanding of SoC architectures. You will own post-silicon validation from first-silicon bring-up through production readiness, working closely with design, pre-silicon verification, firmware, and software teams. This role is hybrid, based out of Austin TX, or Santa Clara CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You are a seasoned post-silicon engineer with 5+ years of experience in SoC bring-up, validation, and silicon debug. You have a strong grasp of CPU and SoC architectures, including RISC-V privilege modes, caches, coherency, and memory systems. You are comfortable debugging complex hardware/software interaction issues using lab tools and low-level software. You thrive in cross-functional environments and enjoy working closely with RTL, firmware, and software teams to solve hard problems. What We Need Lead first-silicon bring-up of RISC-V CPU–based SoCs and execute post-silicon validat

About the Team The Integrity team builds the systems that protect OpenAI’s products, users, and ecosystem from abuse. We work across product engineering, infrastructure, safety, and operations to detect and prevent harmful, fraudulent, deceptive, and adversarial activity at global scale. As OpenAI builds new ads experiences, we are establishing the integrity foundation that will keep the ads ecosystem safe and trustworthy from the start. This includes protecting advertiser onboarding, detecting unsafe or policy-violating ad content, preventing fraudulent and abusive advertiser behavior, and defending the ads ecosystem against spam, manipulation, and other forms of abuse. Ads Integrity is a new and highly cross-functional area. The team partners closely with Ads, Product, Safety, Policy, ML, Privacy, Security, and operations teams to build protections directly into the ads platform rather than layering them on after the fact. This is an opportunity to define how integrity works for a new ads ecosystem from first principles. About the Role We’re looking for an experienced Software Engineer to build the backend systems and infrastructure that keep OpenAI’s ads products safe, trustworthy, and resilient to abuse. In this foundational role, you will design systems that detect, prevent, and respond to harmful, deceptive, fraudulent, or policy-violating activity across the ads lifecycle. The problems span advertiser onboarding and verification, account and behavioral risk, content safety, spam and fraudulent interactions, detection and enforcement infrastructure, and the systems that connect integrity signals and models to real-time product decisions. This is not an ML-specialist role, but familiarity with ML for Ads integrity is always welcome. You’ll work closely with ML engineers and researchers and build systems that consume and operationalize ML-based signals, but your primary focus will be designing and operating robust backend and distributed systems. You’ll help det

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will build the low-level device runtime that turns compiled programs into efficient, functional and performant execution on OpenAI’s custom AI accelerator. This software will schedule kernel launches, manage device memory and address spaces, coordinate synchronization, and expose reliable abstractions to higher-level runtimes and frameworks. You will work at the boundary of software and hardware, partnering with compiler, kernel, architecture, verification, and silicon teams to define interfaces and validate behavior. You will also use and improve event-based, cycle-accurate simulation to develop runtime capabilities before silicon is available, diagnose performance and correctness issues, and guide hardware-software co-design. In this role, you will: Design and implement the low-level device runtime for OpenAI custom silicon. Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling. Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetime across concurrent workloads. Implement synchronization primitives, events, barriers, streams, and ordering guarantees that are correct and efficient. Define clean interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems. Use event-based, cycle-accurate simulators to develop, validate, debug, and performance-tune runtime behavior before and after silicon availability. Di

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . We are looking for a Staff Machine Learning Engineer to lead the technical vision for our Ads Conversion Core Modeling team, building the state-of-the-art systems that power our global marketplace. What you’ll do: Lead the technical direction and development of state-of-the-art applied ML projects for ads conversion. Design and build large-scale DNN models to improve user action prediction with low latency. Mine text, visual, and user signals to better understand intention and infer interests from online activity. Use AI to accelerate analysis and iteration, while applying judgment and verification to ensure correctness and quality. Automate repeatable tasks such as documentation, reporting, and QA checks to speed up the development lifecycle. Coach and mentor engineers whi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years or MSEE with 5+ years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power design methodologies, including UPF-based power inten