Dram Ip Development Layout Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. SUMMARY: At Micron , we are transforming how the world uses information to enrich life for all. As a Layout Design Engineering Intern, you will contribute to the development and verification of selected IP layout cells used in memory products. Working alongside experienced layout engineers, you will gain hands-on experience with industry-standard layout methodologies and participate in key activities such as floorplanning, placement, routing, and physical verification. You will also have the opportunity to develop automation solutions that improve engineering productivity, design quality, and efficiency through scripting and AI-supported development. Responsibilities: Develop the layout of selected analog and digital IP layout cells under the guidance of experienced layout engineers. Perform Design Rule Check (DRC) and Layout Versus Schematic (LVS) verification and document findings. Create and deliver technical reports summarizing design work, verification results, and key lessons learned. Design and implement a SKILL-based automation solution to improve layout design or verification processes, increasing engineering efficiency and quality. Support engineering activities through AI-assisted development methodologies and productivity tools. Minimum Qualifications: Student pursuing a Bachelor's degree in Electrical Engineering, Electronics Engineering, Mechatronics, Robotics, Nanotechnology, Computer Engineering, or a rela

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned DRAM product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. Contribute to effective project-management. Plan and detail your layout, presenting material for global teams to review Optimally connect with engineering teams in India, Japan the US, and other global teams to ensure the success of the layout project. Minimum Qualifica

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As a DRAM Design Engineering Group at Micron Technology, Inc. you will be responsible for translating schematics into layout used for the creation of fabrication reticules. You will be required to meet all engineering and process related criteria needed for an assigned Dram product. You will organize and prioritize logistics and resource allocations to meet scheduled deadlines, and proactively develop methodologies for issue resolution. In this role you will work with Design and other engineering groups to apply multiple layout techniques for the design and verification of digital and analog circuits. You will be expected to understand various circuit design protocols, different fab processes, mask generation techniques, and tapeout processes and procedures. Responsibilities: Responsible for Design and development of IP layouts used in DRAM chips. Perform layout verification like LVS/DRC/EM, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/breakthroughs in multiple project environment. G

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Take responsibility for designing digital IP blocks from initial microarchitecture to RTL creation, integration, and supporting physical hardware development. Define and review module interfaces and system-level architecture. Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate RTL design optimization and design‑space exploration Assist in testbench generation and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom methodology for memory design Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis. Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments. Collaborate closely with architecture, design, verification, and physical design / layout teams. Oversee and manage the layout process including floor-planning, placement, and routing. Perform block-level and full-chip verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools. Contribute to cross-group communication to work towards standardization and group success Provide technical mentorship and participate in design and methodology reviews. Drive innovation into the future memory generations and design methodology within a dynamic w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities of your team will include, but are not limited to: 1. Contributing to the development of new DRAM, emerging memory products and IP’s by enabling the overall design, layout, and optimization of Memory/Logic/Analog circuits 2. Supporting design validation & verification, reticle experiments and required tape-out revisions 3. Performing verification processes with modeling and simulation using industry standard simulators 4. Contributing to cross group communication to work towards standardization and group success 5. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure proper manufacturability of product 6. Proactively solicit inputs from Standards, CAD, modeling, Technology Development groups to ensure the design quality and reliability 7. Driving innovation into the future Memory generations within a dynamic work environ

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The DRAM IP Development (IPDEV) team develops critical digital IP solutions that enable next-generation AI, mobile, client, data center, and graphics memory products. Our team is responsible for delivering high-quality DRAM IPs that drive innovation, product performance, and development efficiency across Micron's memory portfolio. As a Senior or Graduate Engineering Intern in DRAM Circuit Design, you will work alongside experienced engineers to develop and validate digital IP circuits used in future DRAM products. This internship provides hands-on experience with RTL-to-GDS design methodologies, custom design and verification flows, silicon learning, and advanced semiconductor development processes. You will contribute to impactful engineering projects while gaining exposure to industry-standard EDA tools, multi-functional collaboration, and AI-enabled engineering workflows. Responsibilities Support the design, development, and verification of digital IP circuits for next-generation DRAM products using RTL-to-GDS methodologies. Perform circuit analysis across process, voltage, and temperature (PVT) corners to evaluate performance, quality, and reliability. Develop automation scripts and leverage Agentic AI, AI-Assisted tools, or Code Assist solutions to improve engineering productivity and design quality. Collaborate with multi-functional engineering teams on design implementation, verification,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking an experience high-speed high-speed IO/Clocking Design Engineering at a Principal/Sr Member of Technical Staff (SMTS) level to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop core strategy and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation resu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal/Member of Technical Staff (MTS) IO/Clock Design Engeer to join our DRAM IP Design team and contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. In this role, you will be responsible for the design, development, optimization, verification, and technical support of these high-speed IPs. You will focus on equalization and bandwidth extension to push the limits of circuit and process performance, analyze IO impairments as well as clock jitter and duty cycle distortion, and assess their impact on DRAM system timing. You will also develop and implement effective engineering solutions to address these challenges. Relocation to Micron headquarter in Boise, Idaho is required for this position. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power design methodologies, including UPF-based power inten

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Within Micron’s Heterogeneous Integration Group (HIG), we are driving the next generation of High Bandwidth Memory (HBM) solutions that power advanced computing and AI applications. Our team brings together experts across design, product development, manufacturing, and ecosystem partnerships to solve complex technical challenges and deliver innovative memory technologies. The Design Development Technical Lead (DDTL) plays a critical role in enabling predictable, high-quality execution across the HBM design lifecycle. As the single-threaded technical program owner for HBM Build, you will coordinate cross-functional teams. You will manage technical dependencies and risks. You will provide clear leadership across build, product, and executive collaborators to ensure successful program delivery. Responsibilities: Lead end-to-end execution of HBM build achievements across DRAM, base die, test vehicles, interposers, IP, and sustaining development efforts Drive multi-functional alignment, manage dependencies, and maintain execution plans to achieve schedule, cost, and quality objectives Lead governance activities including design reviews, program reviews, risk management, and change control processes Partner with foundries, IP vendors, contractors, and procurement teams to resolve execution challenges and support design delivery Own roadmap communication, executive reporting, and collaborator alignment for HBM build programs Minimum Qualifications: Bachelor’s degree in Electri

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern builds use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. Micron is seeking a Design Infrastructure Engineer to build, enable, and scale characterization infrastructure and deliver generated IP to multiple advanced memory and logic developments. This position includes characterizing both standard and custom cells across various process technologies. These encompass Micron internal nodes as well as external foundries, such as TSMC. The position supports multiple HBM product lines, including HBM DRAM dies, Logic dies (JEDEC and custom variants), and advanced 3D HBM architectures. You will work where circuit build, EDA infrastructure, and silicon validation readiness meet. You will develop robust, scalable, and high-quality characterization flows. These flows directly affect timing closure, power modeling, and product quality for next-generation HBM programs. Responsibilities: Develop and sustain scalable infrastructure for standard cell and custom cell characterization, encompassing timing, power, noise, and signal integrity modeling. Build reusable, a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's ASIC Logic Design team develops next-generation ASICs and controller IP that enable industry-leading memory solutions. Working across advanced process technologies, the team collaborates with architecture, analog, verification, physical design, and validation engineers to deliver high-performance, production-ready silicon for future DRAM products. As an ASIC Digital Design Engineer, you will contribute to the design and development of RTL for next-generation DRAM memory controllers and subsystems. You will work in a collaborative engineering environment supporting design implementation, simulation, validation, and chip bring-up activities while leveraging AI-enabled tools to improve productivity and design quality. Responsibilities Design and develop RTL for DRAM memory controllers and subsystem components using SystemVerilog. Collaborate with analog, verification, physical design, validation, and other cross-functional teams to support successful product development. Develop and validate HDL models, support simulation and co-simulation activities, and analyze design functionality and performance. Support chip bring-up, debugging, and validation activities to identify and resolve design issues. Use scripting, automation, and AI-enabled tools to improve design workflows, productivity, and engineering efficiency. Minimum Qualifications 0-2 years of relevant experience through intern

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Verify IP, subsystem, full-chip, and system-level HBM and DRAM designs to ensure functional correctness, performance, power efficiency, and product quality. Develop comprehensive verification plans from architecture and functional specifications in collaboration with architecture and design teams. Create, enhance, and maintain verification environments, UVM testbenches, test suites, and automated regression infrastructures. Define and execute coverage-driven verification strategies to achieve functional, assertion, and code coverage goals. Lead debug and root-cause analysis of complex design issues, drive bug resolution, and ensure verification closure. Apply advanced digital and mixed-signal verification methodologies using industry-standard simulation and verification tools. Drive continuous improvements in verification methodologies, automation, regression efficiency, and AI-assisted verification workflows. Collaborate closely with global design, architecture, product engineering, and system engineering teams to ensure successful project execution. Lead verification efforts for major HBM development programs and mentor engineers through technical leadership and knowledge sharing. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. 10+ years of experience in digital and/or mixed-signal design verification with a proven record of deli

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we build the memory and storage that powers everything from massive data centers to the devices people carry every day. Our DRAM IP Design team shapes the circuits at the heart of these products, carrying innovative designs from concept all the way to silicon. We work across global design, verification, and product teams, and the work we do here helps define where the semiconductor industry goes next! As a Principal Analog Design Engineer, you'll help shape the next generation of Micron's memory products, bringing circuit designs to life and directly influencing their performance, quality, and reliability. You'll partner with design, verification, and product teams around the world, operating with the independence and technical depth expected of a principal engineer. It's a role where your circuit decisions show up in silicon that ships at scale. Responsibilities: Design, optimize, and verify block-level analog and mixed-signal circuits for DRAM Propose, evaluate, and implement new or improved circuit topologies to enhance block PPAC Work with the internal data science team and EDA vendors to leverage agentic AI and AI-assisted design flows for circuit optimization Expand verification coverage to strengthen robustness and mass-production yield Partner with global design groups, guide layout through post-layout simulation, support silicon-to-simulation correlation, and operate independently to define solutions and methods Minimum Qualifications: