Dram Power Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our Vision Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate, and advance faster than ever. Micron is advancing a historic $15 billion investment in semiconductor manufacturing in Boise, Idaho, with DRAM production planned for the second half of the decade. As a global leader in memory and storage solutions, Micron is investing more than $150 billion worldwide over the next decade to expand leading-edge manufacturing capabilities and drive innovation across the semiconductor industry. Join the Boise expansion team and help build the future of semiconductor manufacturing. You will work alongside experienced engineers to develop advanced processes, solve complex manufacturing challenges, and support the production of technologies that power everything from artificial intelligence to next-generation computing systems. Position Overview As a PCVD Process Engineer , you will contribute to the development, optimization, and sustainment of semiconductor manufacturing processes. You will gain hands-on experience in a state-of-the-art fabrication environment, partnering with teams to improve yield, quality, reliability, and productivity. This role offers an outstanding opportunity to apply engineering fundamentals, build technical expertise, and develop a career in advanced semi

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. In HBM HIG (High Bandwidth Memory, Heterogeneous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most ambitious due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, the

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: As a Mixed-Signal Design Engineer in Micron’s Pathfinding Design Team, you will play a key role in crafting next-generation memory technologies. This position involves contributing to defining, developing, and analyzing high-speed logics to operate the memory. These paths span from the memory array to the interface block for memory technologies, including DRAM and emerging memories. You will work on novel concept development, circuit simulation, optimization, and floor planning to enable groundbreaking memory solutions! Responsibilities: Provide technical direction and design implementation for a memory control circuits (both of digital and analog) from the memory array to the interface block. Collaborate closely with physical design teams to ensure timing closure, CDC robustness, and power intent alignment. Demonstrated experience working with custom mixed-signal IC build and development for volatile or nonvolatile memory technology. Experience with modeling and simulation of ICs using HSPICE/finesim. Minimum Qualifications: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field. 7&#43; years of experience in custom mixed-signal circuit design. Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction) </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Senior Verification Engineer with 4-8 years of Experience As a Senior RTL Verification Engineer you will work in a highly innovative, motivated, Upbeat, and dynamic design team capable of verifying complete products using innovative memory technologies. You will need to have the ability to drive the team and the overall verification effort to ensure the timely delivery of a functionally accurate design. Unique Opportunities Complete ownership of RTL verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5,DDR6 and LPDDR6 that can operate at high speeds of up to 9600MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work wi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Unique Opportunities Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5,DDR6 and LPDDR6 that can operate at high speeds of up to 9600MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: Guide and set the direction for the verification effort within your areas of expertise in any project that the team undertakes. Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features. Participate in developing verification methodology and verification environments for sophisticated products. Co-work with international colleagues on developing new verification flows to take on the challenges in design. Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Ability to identify verification pain points sui

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Validation Product Engineer on High Bandwidth Memory (HBM) technology you will be tasked with developing next-generation HBM products. Product Engineers are a key interface between Design, Manufacturing, Test, and Quality internal departments as well as external customers. We take ownership of HBM products; starting at the Design phase, through initial bring-up, qualification, and into volume production. The seniority level offered will be based on a combination of experience and education. In HBM HIG or equivalent experience (High Bandwidth Memory, Heterogeneous Integration Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI. The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, &#34;high bandwidth&#34;; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design on

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DASG Architecture Lab and Customer Enablement Lab (CEL) teams provide the infrastructure, platforms, and technical expertise required to accelerate technology pathfinding, AI and system workload analysis, memory subsystem characterization, FPGA/LPDRAM prototyping, and customer enablement initiatives. These teams play a critical role in enabling architecture exploration, validation, and teamwork across engineering organizations and external partners. AI Efficiency and Usage is a must. AI proficiency or AI‑enabled ways of working where applicable. Agentic AI and Generative AI usage model is a must. Responsibilities Own the day-to-day bring-up, readiness, maintenance, and operational support of lab systems, racks, benches, test equipment, and reference platforms used by DASG Architecture Lab and Customer Enablement Lab teams. Deploy, configure, and maintain server, GPU, FPGA, client AI, mobile AI, analyzer, and environmental test equipment supporting workload characterization and technology pathfinding activities. Build and maintain stable, reproducible validation environments, including BIOS, BMC, firmware, operating systems, drivers, networking, remote access, and power and thermal configurations. Collaborate with architecture and validation teams to enable memory trace capture, workload analysis, DRAM replay, power and performance characterization, and data-driven engineering decisions. Develop and maintain operational processes for asset tracking, configuration management, equipme

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. High-bandwidth memory (HBM) is an innovative memory solution that uses 3D stacking of DRAM for fast speeds, expansive bandwidth and low power per transaction. HBM is primary solution for AI applications. As a Micron Global Quality FE Central (Senior) QE Product Engineer, you will be a member of the worldwide quality team, responsible for driving quality and reliability initiatives into FE MFG network for high bandwidth memory (HBM) product for critical customer AI applications. You will work closely with PE/GQ QRA/FE fab teams and Central PIE to establish BKMs, set up program with line of sight metric, develop a strategy and closely work on execution to achieve program milestones for customer field DPM excellence. You will also work with smart manufacturing AI team for automation and AI solution development and deployment to continue helping HBM quality management with AI transformation. Responsibilities and Tasks: <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8&#43; years of experience, or Bachelor’s degree with 10&#43; years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. This role will drive physical design execution from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis, and design reliability. The engineer will collaborate across architecture, RTL, implementation, CAD, and technology teams to develop scalable physical design solutions that achieve power, performance, area (PPA), and reliability targets for next-generation memory products. Additionally, this individual will lead methodology innovation, mentor engineers, and influence the future roadmap for physical design and power integrity across the organization. Responsibilities Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout activities. Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, electromigration (EM) verification, and EMIR signoff. Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at both block and full-chip levels. Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability. Mentor engineers and provide technical leadership while influencing future memory products t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8&#43; years of experience, or Bachelor’s degree with 10&#43; years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power design methodologies, including UPF-based power inten

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop DRAM digital and mixed-signal blocks for advanced memory products. In this role, you will support the RTL lifecycle from specification and implementation to signoff. You will collaborate with multi-functional teams to develop high-quality builds that meet power, performance, and area (PPA) targets. This position is based in Boise, Idaho, within a collaborative and innovative engineering environment. Responsibilities Contribute to RTL build of digital and mixed-signal components for DRAM using RTL-to-GDS flows. Implement and document high-performance, power- and area-efficient RTL designs meeting product specifications. Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design and implementation teams to achieve timing closure and PPA goals. Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk. Minimum Qualifications Master’s degree in Electrical Engineering with 4&#43; years of experience, or Bachelor’s degree with 5&#43; years of pre-silicon RTL design experience. Demonstrated experience developing RTL for complex digital IP from specification through implementation handoff. Hands-on experience with ASIC low-power design methodologies, including UPF-based power intent and CDC/RDC analysis. Strong knowledge of ASIC design flows, including RTL design, logi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, we transform how the world uses information to enrich life for all. The Heterogeneous Integration Group (HIG) HBM Architecture team develops next-generation High-Bandwidth Memory (HBM) solutions that power AI, high-performance computing, cloud infrastructure, and advanced networking systems. The team works across architecture, design, verification, packaging, product engineering, and technology development to evaluate innovative memory architectures and deliver scalable, high-performance semiconductor solutions. As an HBM Design Architect, New College Graduate, you will contribute to the evaluation and development of future HBM and DRAM architectures. Working with experienced architects and engineering teams, you will analyze system and block-level design tradeoffs related to performance, power, area, thermal behavior, reliability, and manufacturability. This role provides an opportunity to leverage AI, Large Language Models (LLMs), and data-driven engineering methodologies to accelerate architecture exploration and improve decision-making. Responsibilities Analyze HBM and DRAM architectures using analytic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7&#43; years or MSEE with 5&#43; years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Contribute to the development of new product opportunities by assisting with the overall design, layout, and optimization of DRAM Memory array/Peripheral Logic/Analog circuits Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate schematic optimization and design‑space exploration Assist in parasitic analysis, sensitivity studies, and corner coverage Improve debug efficiency across simulation and silicon learning loops Define semicustom methodology for memory design Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments. Oversee and manage the layout process including floor-planning, placement, and routing Perform circuit-level verification including functional, timing, power and reliability analysis using industry standard and Micron-specific simulators and tools. Contribute to cross-group communication to work towards standardization and group success Drive innovation into the future memory generations and design methodology within a dynamic work environment Minimum Qualifications Master’s degree in electrical or computer engineering with 15&#43; years of experience in vlsi design. Strong fundamentals in CMOS circuit design, device physics and memory operation. Proven lea