Dram Technology Transfer Process Integration Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology has delivered world‑leading memory and semiconductor solutions. As an HBM Memory Design Engineer on the HBM Architecture Team, you will design, simulate, optimize, and floorplan advanced DRAM circuits for next‑generation High Bandwidth Memory products. You will work across digital, analog, and mixed-signal domains to ensure functional correctness, performance, and power efficiency. Your role includes collaborating with globally distributed teams developing modern HBM solutions for AI and ML applications. Responsibilities • Design, simulate, and optimize DRAM memory arrays, data paths, ECC, command/control logic, and high‑speed interface circuits • Evaluate block‑level and full‑chip functionality and propose solutions to ensure functional correctness • Analyze timing, area, power, and complexity trade‑offs in high‑speed DRAM and mixed‑signal designs • Perform pathfinding and feasibility studies for new architectures and future HBM products • Contribute to the design, layout, and optimization of memory, logic, and analog circuits • Support large‑scale verification, debug, and silicon validation activities • Collaborate across multi-functional teams involved in TSV‑based 3D stacking and vertical integration • Participate in design reviews and drive continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years or MSEE with 5+ years of relevant engineering experience • Strong knowledge of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Memory Design Engineer in Micron’s HBM Architecture Team, you will design, simulate, analyze, and floorplan digital and analog DRAM circuits used in advanced HBM technology. You will evaluate block-level and full-chip functionality, perform architectural pathfinding, and contribute to the development of next‑generation high‑bandwidth DRAM solutions. This role works across diverse engineering teams to deliver functionally accurate, low‑power, and high‑performance HBM products by bringing to bear 3D stacking and TSV-based integration. Responsibilities • Design, simulate, and optimize digital and analog DRAM circuits including data path, ECC, command/control, and high‑speed timing structures • Evaluate full‑chip and block‑level functionality and propose solutions to achieve correct circuit and system behavior • Perform timing, area, power, and complexity analysis for high‑speed DRAM and mixed‑signal circuits • Conduct pathfinding studies and feasibility analyses for future HBM architectures • Contribute to the development, layout, and optimization of memory, logic, and analog circuits • Analyze circuit behavior under varying PVT and parasitic conditions to ensure robust operation • Collaborate with multi-functional teams across build, verification, product engineering, process, and packaging • Support design reviews, documentation, and continuous improvement of design methodologies Minimum Qualifications • BSEE with 7+ years, or MSEE with 5+ years of releva

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron Technology is seeking a Principal RTL Design Engineer to lead the development of high-quality DRAM digital and mixed-signal IP. In this role, you will be responsible for the full RTL design lifecycle—from architecture and implementation through signoff—while delivering designs that meet aggressive power, performance, and area (PPA) targets. This position is in Boise, Idaho, offering strong opportunities for technical leadership, innovation, and collaboration across global teams. Responsibilities Own and drive RTL design for DRAM digital and mixed-signal IP from specification through silicon-ready signoff. Architect and deliver high-performance, power- and area-efficient RTL designs aligned with product requirements. Perform and sign off front-end quality checks, including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design, verification, and architecture teams to achieve timing closure and PPA goals. Improve design quality and efficiency by refining methodologies, driving automation, and enhancing RTL design flows. Minimum Qualifications Master’s degree in Electrical Engineering with 8+ years of experience, or Bachelor’s degree with 10+ years of pre-silicon RTL design experience. Proven ownership of complex RTL/IP development from micro-architecture definition through handoff to physical design. Strong experience with ASIC low-power design methodologies, including UPF-based power inten

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop DRAM digital and mixed-signal blocks for advanced memory products. In this role, you will support the RTL lifecycle from specification and implementation to signoff. You will collaborate with multi-functional teams to develop high-quality builds that meet power, performance, and area (PPA) targets. This position is based in Boise, Idaho, within a collaborative and innovative engineering environment. Responsibilities Contribute to RTL build of digital and mixed-signal components for DRAM using RTL-to-GDS flows. Implement and document high-performance, power- and area-efficient RTL designs meeting product specifications. Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design and implementation teams to achieve timing closure and PPA goals. Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk. Minimum Qualifications Master’s degree in Electrical Engineering with 4+ years of experience, or Bachelor’s degree with 5+ years of pre-silicon RTL design experience. Demonstrated experience developing RTL for complex digital IP from specification through implementation handoff. Hands-on experience with ASIC low-power design methodologies, including UPF-based power intent and CDC/RDC analysis. Strong knowledge of ASIC design flows, including RTL design, logi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description: As a Mixed-Signal Design Engineer in Micron’s Pathfinding Design Team, you will play a key role in crafting next-generation memory technologies. This position involves contributing to defining, developing, and analyzing high-speed logics to operate the memory. These paths span from the memory array to the interface block for memory technologies, including DRAM and emerging memories. You will work on novel concept development, circuit simulation, optimization, and floor planning to enable groundbreaking memory solutions! Responsibilities: Provide technical direction and design implementation for a memory control circuits (both of digital and analog) from the memory array to the interface block. Collaborate closely with physical design teams to ensure timing closure, CDC robustness, and power intent alignment. Demonstrated experience working with custom mixed-signal IC build and development for volatile or nonvolatile memory technology. Experience with modeling and simulation of ICs using HSPICE/finesim. Minimum Qualifications: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or related field. 7&#43; years of experience in custom mixed-signal circuit design. Proficiency with UNIX and CADENCE design environment (Simulation, Schematic entry, SPF extraction) </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary This position supports Micron’s DRAM Tester Solutions group, focusing on physical design implementation for processors, controller architectures, and ASICs. The role is responsible for full‑chip and block‑level physical design closure, low‑power implementation, timing, power, and signal integrity signoff, and successful tape‑out across advanced technology nodes. Responsibilities: Lead block‑level and full‑chip physical design including floorplanning, placement, CTS, routing, and tape‑out. Drive timing closure across multiple modes and corners using industry‑standard STA tools. Perform power integrity, IR/EM, and power grid closure to meet signoff requirements. Develop and optimize APR flows, scripts, and methodologies for PPA improvements. Own subsystem or full-chip closure work while coordinating with cross-functional teams. Minimum Qualifications: Bachelor’s degree or Master’s degree or equivalent experience in Electrical Engineering, Electronics, or Computer Architecture. Minimum of 15 years of hands‑on ASIC physical design implementation experience. Proven experience with multiple production tape‑outs in advanced process nodes. Strong expertise in low‑power design techniques including UPF/CPF and multi‑voltage systems. Proficiency in scripting languages such as Tcl, Perl, or Python for flow automation. Preferred Qualifications: Experience with Synopsys and Cadence physical design and ti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Frontend Central Product Integration Engineering (PIE) team delivers best‑in‑class yield, quality, and cycle time through innovation and strong cross‑functional teamwork. Supporting diverse DRAM and NAND technologies across global development and manufacturing sites (Boise, Japan, and fabs in the U.S., Taiwan, Japan, and Singapore), the team identifies, aligns, and deploys best‑known methods across the network. As a Frontend Central Process Integration Senior Engineer, you will develop and optimize processes to drive rapid product maturity. Join us today and make a difference! Responsibilities and Tasks Drive rapid product maturity, improving yield (bits per wafer), repair density, and DPM through fast learning cycles. Apply deep process integration knowledge across FEOL, MOL, CELL, and BEOL to identify optimal solutions; design and circuit knowledge is a plus. Partner with Yield Engineering, Device, RDA, and Metrology teams to resolve key yield issues and build strong inline visibility for fast ramp and excursion prevention. Identify and standardize best‑known methods and business processes across DRAM and NAND sites. Travel to Micron sites as needed for onsite collaboration. Minimum Qualifications Bachelor’s degree in Engineering or a related field 5&#43; years of experience in process integration, product design, or equivalent technical roles Demonstrated ability to collaborate optimally with global, cross‑functional teams Proven t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. A thorough understanding of semiconductor device physics, process operation, DRAM product specification and product reliability. Responsibilities include but are not limited to the following: rdV, UE_Row, PG, PTS yield improvement Burn dpm and module dpm improvement DL4 enhancement and shift left to probe for coverage MRB case management and postmortem for CAPA enhancement Fab deviation event disposition and hold lot release Product grade yield improvement Wafer level reliability monitoring and shift left to probe for coverage RMA management and analysis for process/probe improvement Problem solving and root cause analysis skills including developing systemic and specific CAPAs for RMA Monitors and drives the quality metrics improvements including, module production fails and RMAs. Monitor Global quality dashboard and report reliability metric not meeting spec and performance Leads the analysis of multiple data sources and ensures appropriate feedback is given to customer Working in collaboration with multiple engineering groups including Process Module Area/RDA/Manufacturing to help identify existing containment action and work towards continuous improveme

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: • Establish and improve process condition and technology. • Upgrade process capability and reduce production cost. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more, please visit micron.com/careers All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status. To request assistance with the application process and/or for reasonable accommodations, please contact <a target="_blank" href="mailto:hrsupport_jp&#64;micron.c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As RAM Detection (RDA and Metrology) Detection Strategy Senor Engineer/ Principal Engineer at Micron Technology, Inc., you will be collaborating with process, equipment, as well as process integration team, responsible for starting up, developing and optimizing detection to improve product yield, quality, and cost! Responsibilities include working closely with the NAND and DRAM sites, HVM and TD, and even suppliers, to achieve Inline Visibility and Inline Control for Detection enablement and improvement. This position is responsible in setting up BKM (Best Known Method) related to RAM Detection performance, RAM detection cost and RAM supplier engagement. This position also ensures BKM alignment and deployment, hence RAM Standardization across sites! What’s Encouraged Daily: Lead Detection SWAT (System Workforce Allocation Team) in identifying BKM and strategies to meet Detection goal Lead RAM network in BKM standardization across all sites Develop metrics and KPI to measure success and performance of the team Lead a team of engineers in projects, see opportunities and risks, and find solutions to clear roadblocks. Devise strategy, plans and roadmap for team for short term and long term Apply organizational skill in job assignment and task allocation Prioritize resources in the team to accomplish goals. Maintain good working relationship with partn

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a DRAM and Emerging Memory Quality and Reliability Assurance (DEMQRA) High Bandwidth Memory (HBM) Engineer at Micron Technology, Inc., your primary responsibility will be establishing quality criteria and monitoring quality indices based on FE and BE signals from NPI to high-volume manufacturing (HVM). You will define, lead and drive key action to bring Micron product quality to be the best in class and to prevent quality and reliability related issues from repeat occurrence. Meanwhile, you will involve in developing and supporting qualification stress flows and characterization for HBM and other high performance memory solutions. You will be driving the following: Collaborate with collaborators to define, deploy and monitor outgoing quality and reliability (OQR) metrics based on FE and BE production signals as well as reliability test results Partner with package development engineer and product engineer on latest products and technologies to define quality and reliability fail modes Proactively work to evaluate, characterize, and mitigate Quality and Reliability risks and fail modes for BE new products and HVM Collaborate with MFG Quality Assurance and Quality Engineer teams to improve QR fail mode list for HVM products. Engage with key teams to set and validate OQR specifications and address recognized and potential Quality and Reliability issues Dispo deviation material based on production signals and reliability test results with quick turnaround ti

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow Hands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of industry standard tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice and Micron-specific simulators Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments and contribute to cross-group communication to work towards standardization and group success About