Engineer 6 Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior/Staff Engineer in CPQE Deviation Management at Micron Technology, Inc., you will have a meaningful role in advancing quality excellence throughout Micron’s global Frontend manufacturing network. The mission of the Central QE organization is to raise Micron’s quality standards through focused collaboration with manufacturing sites, Global Quality teams, and Central partners. Join our driven team and contribute to the pursuit of flawless quality management! Key Responsibilities Lead global quality initiatives to build, implement, and sustain robust deviation management processes and systems. Drive the Issue Tracker SWAT team, deploying Best-Known Methods (BKMs) and standardizing practices across manufacturing sites. Analyze and resolve minor deviations (e.g., yield spread, yield deviation & minor GPSS) by providing data-driven recommendations to improve fab performance. Drive quality improvement efforts, resolving non-conformances and introducing corrective and preventive steps. Continuously improve quality metrics such as $CoNC and %NCD through innovative solutions and system improvements. Form and lead cross-functional task forces to address quality health concerns and improve metric performance across sites. Drive innovative, AI-powered project solutions to optimize efficiency, accelerate problem resolution, and deliver sustained benchmark performance. Set up key Quality program from planning stage and well verse with deployment and proliferation strategy in the

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Location Micron Singapore Bendemeer (990 Bendemeer Road, SIngapore 339942) Department MSB Test Solutions Engineering Project Title NAND Component Test Flow Optimization Using AI-Enabled Data Analytics and Automation Project Description The intern will participate in a structured Product Development Engineering project focused on optimizing NAND component test flows using manufacturing data analytics, automation, and Artificial Intelligence. Under appropriate guidance, the intern will develop analytical tools, models, and visualizations to study manufacturing data, identify product recovery opportunities, and improve test-flow efficiency. The project will provide practical exposure to data engineering, statistical analysis, machine learning, prompt engineering, and the responsible application of enterprise AI tools. Objective of the Project The project aims to: Improve the analysis of manufacturing and test-flow data. Identify data-driven opportunities to enhance product recovery. Develop automation solutions that improve engineering analytical efficiency. Apply statistical, machine learning, and AI-Enabled methodologies to generate actio

Our Purpose Mastercard powers economies and empowers people in 200+ countries and territories worldwide. Together with our customers, we’re helping build a sustainable economy where everyone can prosper. We support a wide range of digital payments choices, making transactions secure, simple, smart and accessible. Our technology and innovation, partnerships and networks combine to deliver a unique set of products and services that help people, businesses and governments realize their greatest potential. Title and Summary Senior AI Engineer, Big Data & AI Solutions Overview The Security Solutions Data Science team develops AI and machine learning capabilities that help protect the global payments ecosystem from fraud and cyber threats. Supporting Mastercard’s Safety Net product, the team develops and enhances models that analyze billions of transactions and identify suspicious activity. As a Senior AI Engineer, you will work at the intersection of big data engineering and AI/ML, helping build and support the data, features, models, and production processes behind fraud detection. Ideal Candidate Profile You are a big data and AI/ML engineer who has used Apache Spark in a professional environment and has hands-on experience working within CI/CD-driven engineering environments. You understand how large-scale data moves from raw inputs through data and feature pipelines into machine learning models, and how those models are deployed, monitored, and improved in production. Large-scale data → Spark/PySpark → Data & Feature Pipelines → ML models → Production Deployment→ CI/CD→Monitoring & Drift Detection → Optimization & Retraining Experience with Generative AI, RAG, LLMs, or agentic AI is valuable, but the foundation for this role is large-scale data engineering and production AI/M

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for a Senior Software Performance Engineer for Autonomous Vehicles! Our team builds NVIDIA’s end-to-end autonomous driving applications. We are seeking senior software engineers who are passionate about performance with an interest in optimizing self-driving solutions that run on NVIDIA’s multi-computer and heterogenous HW architectures. What you’ll be doing: Develop, maintain and optimize latency and throughput of NVIDIA’s L2/L3/L4 autonomous driving solutions. Devise acceleration strategies and patterns to improve software architecture and its efficiency on our computers with multiple heterogeneous hardware engines while meeting or exceeding product goals. Develop highly efficient product code in C++, making use of algorithmic parallelism offered by GPGPU programming (CUDA)/ARM NEON while following quality and safety standards such as defined by MISRA. Collaborate with HW, product, OS, and safety teams to design next-gen products. What we need to see: MS or PhD degree in Computer Science, Computer Architecture, Electrical Engineering or related field (or equivalent experience). 12+ years of relevant professional experience. Excel

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a member in our team, you will own and work with cross functional teams, implementing state-of-the-art designs in test access mechanisms, IO BIST, memory BIST and scan compression. In addition, you will help develop and deploy DFT methodologies for our next generation products. You will have the chance to define, prototype and deploy next generation DFX architectures and methodologies across all our products. This includes high speed test access architectures, the in-system-test architecture, ISO26262 functional safety diagnostic for in-field testing and beyond, silicon debug & bring-up, productization, and silicon life-cycle management among others As a member on our DFX Architecture team, your responsibility will be to craft key DFX architecture and methodologies to meet system level safety diagnostic test quality, in-field test quality, advanced defect screening and diagnosis to enable SLM for automotive, industrial, and robotics safety platforms etc. Collaborate with multi-functional teams like system architecture, chip architecture, ASIC design, verification, CAD, VLSI,

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding opportunity to join a world-class team and make a significant impact in the semiconductor industry! What You'll Be Doing: Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms. Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST, memory BIST, and scan compression. Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology. Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre-silicon through production deployment. Develop and standardize methodologies, processes, and workflows for silicon bring-up, crafting reusable checklists and playbooks. Improve cross-team communication, work, and handoffs. Guide and mentor junior engineers, helping them navigate complex build trade-offs to achieve world-class quality and efficiency. What We Need To See: BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains. Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation. Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate builds using vendor tools. Experience in silicon debug and bring-up with an understanding of pattern formats, failure processing, and test program development. Strong programming and scripting skills. Excellent written and or

As a member of the HW Infrastructure Storage Strategy team, you will be the bridge between storage infrastructure and the chip design (e.g. NVIDIA GPUs and CPUs) workloads that depend on it. You will focus on going hands-on to understand how storage behavior impacts EDA (Electronic Design Automation) and HPC workload performance in general — and what to do about it. You’ll evaluate next-generation storage technologies, design POCs grounded in real workload profiles, uncover gaps in observability, and drive strategic decisions like data placement during datacenter transitions. This is a rare role where you’ll work at the intersection of storage systems and chip design workflows at a scale few companies reach — petabytes of active data, millions of files per job, and thousands of concurrent users. You’ll develop NVIDIA’s storage strategy and have a direct, measurable impact on engineering velocity. What you'll be doing: Lead storage technology evaluations — design and execute POCs for platforms such as NetApp, VAST, and others, using real EDA workload profiles to benchmark performance, metadata behavior, and compatibility Analyze how storage configurations and architecture choices impact EDA workload runtime in production, and recommend tuning or architectural changes to reduce job execution time Identify gaps in storage telemetry and observability — define what metrics are needed and how to correlate storage behavior with jobs running on the environment Support datacenter lifecycle programs — expansions, technology refreshes, and site exits — by mapping workload placement, identifying required data, and minimizing data replication scope Define storage policies and best practices — data lifecycle, tiering strategies, snapshot/clone workflows (e.g., FlexClone for EDA workspace branching), and capacity planning recommendations Collaborate with IT, EDA tool teams, EDA operations, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Boise Expansion Team is helping build the future of semiconductor manufacturing as Micron expands its leading-edge memory production in Boise, Idaho. We are a collaborative organization focused on innovation, operational excellence, and continuous improvement. Join a team where your work will directly influence product quality, manufacturing performance, and the next generation of technology. As a Yield Analysis Engineer, you will play a key role in improving fab yield through advanced data analysis, defect characterization, and root cause investigation. You will work closely with Process Integration, Process Engineering, and Failure Analysis teams to identify yield limiters, drive corrective actions, and deliver sustainable yield improvements. This role offers the opportunity to combine semiconductor expertise, analytics, and AI-enabled tools to solve complex manufacturing challenges. Responsibilities: Monitor probe yields and trends to identify yield excursions, characterize yield loss, and explain gaps between target and actual performance Perform advanced data analysis and develop yield paretos to prioritize issues and guide factory yield-improvement efforts Apply statistical methods and data-mining techniques to identify root causes and uncover opportunities for process improvement Partner with Failure Analysis, Process Integration, and Process Engineering teams to correlate electrical, physical, and manufacturing data and drive issue resolution Develo

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in the world—spanning 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs powering Autonomous Machines, Robotics, and Industrial systems. You will innovate at scale, designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that consistently delivers breakthrough performance across multiple high-impact tape-outs each year. What you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms. Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions. Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio. Guide and mentor junior engineers, helping them navigate complex design

NVIDIA’s GPUs and SOCs are the world leaders in power, performance, and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Mask Design Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Package Technical Lead and different design teams in designing and developing sophisticated, detailed layout of silicon interposers for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: You'll collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule. Performing physical layout for silicon interposer using Cadence tools. Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance. Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists. Propose layout design trade-offs to the PTL for resolution and implementation. What we need to see: Hold a B.S. Electrical Engineering or equivalent experience Minimum of 5+ years proven experience in Mask and Layout Design. Deep understanding of layout concepts in submicron CMOS technologies. You are an authority with Cadence layout tools - particularly Virtuoso. Knowledge of Integrity auto-routing is a plus. Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc. Proficient in scripting languages like Perl, Python, S

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We’re building the next generation of DRAM technology and pushing what’s possible at the intersection of device physics and circuit design. Our team thrives on solving deep technical challenges and turning innovative ideas into high-performance, manufacturable memory solutions. If you’re excited about influencing future technology nodes and working on designs that ship at scale, you’ll feel right at home with us! As a Staff DRAM Design Engineer, you’ll play a critical role in shaping memory architectures and circuit innovations that directly impact product performance, power, and reliability. This is a hands-on design role where your expertise will drive key decisions from concept through silicon validation, while collaborating with cross-functional teams to deliver meaningful results. Responsibilities: Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic Perform and analyze circuit simulations using tools such as SPICE and Verilog Evaluate architectural trade-offs impacting power, performance, and die size Integrate layout parasitics into simulations and drive design for manufacturability Define validation strategies including test chip development and silicon bring-up Minimum Qualifications: Bachelor’s degree in Electrical Engineering or related field 5+ years of circuit design experience or product engineering experience Strong understanding of analog and digital circuit fu

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role As an Applied AI Engineer on the Startups team at Anthropic, you will be a trusted technical advisor to the top AI-native startups building in the physical world, across robotics, semiconductors, aerospace, manufacturing, and civil infrastructure, as they grow from early product to scale. Some of these companies build the hardware itself and want Claude woven into how they design, test, and operate it, and others build the software that engineers everywhere use to design, simulate, test, and scale, and this role works with both. You'll lead deep technical engagements, partnering directly with startup software and hardware engineering teams to help them build their products on Claude and run their own engineering with it, advising on implementation and agent design as they build what is newly possible with AI in the physical world. You will bridge the gap between what Claude can do and what it takes to build real things, working alongside some of the strongest teams in the field on problems that matter and helping mechanical, electrical, and process engineers get the kind of step change that software engineering has had from agentic coding with tools like Claude Code. Working closely with Applied AI Architects, Account Executives, and Anthropic's Product, Engineering, and Research teams, you'll help startups build at the edge of what is possible with Claude. You'll leverage your AI engineering expertise and your engineering domain knowledge to develop custom evaluation frameworks, design scalable architectures, and create the technical resources that enable physical AI startups to succeed with Claude. Responsibilities Se

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role As an Applied AI Engineer on the Startups team at Anthropic, you will be a trusted technical advisor to the top AI-native life sciences and biotech startups as they grow from early product to scale. Some of these companies build products on Claude that they sell to the rest of the industry, and others do the science themselves and want Claude woven into how their own research runs, and this role works with both. You'll lead deep technical engagements, partnering directly with startup engineering and scientific teams to help them build their products on Claude and run their own research with it, advising on implementation and agent design as they build what is newly possible with AI in the life sciences. You will bridge the gap between what Claude can do and what the life sciences need, working alongside some of the strongest teams in the field on problems that matter and pushing the boundaries of AI in science as you go. Working closely with Applied AI Architects, Account Executives, and Anthropic's Product, Engineering, and Research teams, you'll help startups build at the edge of what is possible with Claude. You'll leverage your AI engineering expertise and your scientific domain knowledge to develop custom evaluation frameworks, design scalable architectures, and create the technical resources that enable life sciences startups to succeed with Claude. Responsibilities Serve as a deep technical advisor to high-potential life sciences and biotech startups, whether Claude sits inside the product they sell or inside the way they make discoveries, working alongside them to build innovative use cases that push the boundar

EMPLOYER IS A CONTRACTOR FOR THE U.S. GOVERNMENT. THIS POSITION REQUIRES U.S. CITIZENSHIP. Role Description: Defense Unicorns is seeking a Senior Platform Engineer to join our Army team, focused on building and operating product-aligned platform capabilities that enable how our software is developed, validated, and experienced. This role is responsible for creating and owning persistent, always-on environments and integration layers across the UDS platform, including Fleet Management, Edge Management, and system-level components. These environments power internal dogfooding, UX validation, and customer demos, reducing reliance on ad-hoc local setups and enabling scalable, repeatable and delightful product experiences. Today, engineers are frequently pulled into demo setup and environment management of the suite of products, creating context switching and slowing product delivery. This role exists to solve that problem by establishing reliable, self-service environments and tighter system integration, allowing engineering teams to focus on building product capabilities while improving overall product quality and usability. You will operate at the intersection of platform engineering and product development, ensuring that the systems we build can be continuously exercised, validated, and experienced in real-world conditions. You will be responsible for advocating for a delightful customer product experience as the integrator of the product portfolio. What You'll Work On: Designing and operating always-on product environments for customer demos, internal use, and stakeholder access Building feature branch / preview environments to support UX and rapid feedback loops Enabling internal dogfooding through real, long-running deployments of UDS products Integrating core system components across Fleet Management, Edge Management, OS, and related services Reducing reliance on local environments by creating shared, reproducible infrastructure Supporting pathw