Hardware Software Codesign Engineer Jobs

Chez Lyft, notre mission est de servir et de connecter. Nous y parvenons en favorisant un environnement de travail où chacun trouve sa place et a la possibilité de s'épanouir. Lyft connecte les gens aux transports pour transformer notre façon de vivre et de nous déplacer dans nos communautés. Solution Urbaines de Lyft (LUS) est le leader nord-américain de la micromobilité. Nous possédons, exploitons ou fournissons des solutions matérielles et logicielles pour les programmes de vélos et de trottinettes en libre-service dans plus de 57 marchés à travers le monde, notamment à Montréal, Londres, New York, Mexico et bien d'autres villes. Notre flotte en pleine expansion comprend des stations de recharge ultramodernes, des vélos et des trottinettes électriques, et assure des centaines de millions de trajets par an. L'équipe de conception de produits matériels et industriels de LUS est chargée de concevoir, de piloter le développement, de lancer et de maintenir des produits de pointe utilisés par les usagers, les villes et les opérateurs du monde entier. Nous représentons LUS lors des forums de micromobilité, interagissons directement avec les clients et orientons la recherche et le développement. Notre objectif est de garantir que tous les produits que nous développons offrent une expérience utilisateur optimale, soient compétitifs à l'échelle mondiale, élégants et tournés vers l'avenir. Nous recherchons un chef de produit matériel senior exceptionnel pour gérer notre portefeuille de stations existantes et développer la prochaine génération de produits. Nos stations sont aujourd'hui aussi emblématiques du paysage urbain que les anciens bus Routemaster londoniens. Vous serez responsable de l'ensemble du processus de développement des nouvelles stations, en pilotant une équipe pluridisciplinaire à chaque étape, du développement matériel au lancement. Vous gérerez également un parc de plus de 300 000 stations, avec ou sans chargeur, déjà déployées. Vous collaborerez directem

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE As a Hardware Manufacturing Test Engineer at Everpure, you will spearhead manufacturing test enablement for our next-generation enterprise hardware platforms from New Product Introduction (NPI) through high-volume production ramp. Operating with high autonomy, you will design robust test strategies and collaborate cross-functionally with Firmware, Diagnostics, and global factory teams to deliver market-ready, high-yield hardware infrastructure. Your expertise will directly optimize manufacturing throughput, improve release quality, and accelerate the global deployment of the industry-defining Everpure Platform. WHAT YOU'LL DO Own NPI & Sustaining Test Readiness: Drive end-to-end manufacturing test strategy, test sequence definition, and coverage validation for multiple hardware infrastructure variants to ensure seamless factory execution and build readiness. Lead Debug & Yield Optimization: Independently lead technical triage and resolve complex system-level test fallout during critical build phases, analyzing failure paretos to isolate root causes across hardware, firmware, and test infrastructure. Scale Test Architecture & Frameworks: Enhance and standardize the Design for Manufacturing (DFM) hardware test architecture by deploying reusable automation frameworks and consolidating test execution into shared platforms to minimize factory cycle times. Drive Vendor & Cross-Functional Alignment: Colla

Manufacturing Test Engineer – Server Hardware Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Austin, which will play a central role in Graphcore's work building the future of AI computing. Role Overview We are seeking an experienced Manufacturing Test Engineer to support high-volume server manufacturing from board-level test through system-level production test. This role will work closely with an ODM manufacturing partner to define, implement, validate, and optimize the manufacturing test strategy for L6 board-level products , including ICT, MDA, and Board Functional Test , as well as support L10 system-level manufacturing test . The ideal candidate has strong experience in server hardware manufacturing, Linux-based test environments, diagnostic test coverage, fixture requirements, yield improvement, and root cause corrective action processes. This role requires both technical depth and hands-on manufacturing execution experience, with the ability to drive best practices across test development, factory readiness, quality planning, and ongoing production support. Key Responsibilities Manufacturing Test Strategy and Planning Work with ODM partners to define and execute the manufacturing test strategy for L6 board-level production . Develop and review test plans covering: In-Circuit Test, or ICT Manufacturing Defect Analyzer, or MDA Board Functional Test Diagnostic coverage requirements Manufacturing line test flow Fai

About the Team The Stargate team is responsible for building the physical infrastructure that powers large-scale AI systems. We design and deliver next-generation data centers optimized for dense compute clusters, advanced networking, and rapidly evolving hardware platforms. This work sits at the intersection of hardware engineering, systems architecture, and infrastructure execution—translating cutting-edge compute roadmaps into scalable, production-ready environments. Our teams partner across silicon vendors, server and storage OEMs, networking teams, and data center engineering organizations to bring new capacity online quickly, reliably, and at global scale. About the Role We are seeking a CPU & Storage Technical Lead to define and drive the server compute and storage architecture strategy for Stargate infrastructure. In this role, you will own technical direction across CPU platforms, memory configurations, local and disaggregated storage systems, and their integration into large-scale AI clusters. You will evaluate vendor roadmaps, lead platform tradeoff decisions, and ensure compute and storage systems are optimized for training, inference, and supporting services. You will work cross-functionally with hardware engineering, performance modeling, networking, supply chain, and deployment teams, as well as external partners such as AMD, Intel, OEMs, ODMs, and storage vendors. This is a highly strategic role for someone who can operate deeply at the component level while also driving long-range infrastructure decisions. Key Responsibilities Own CPU and storage technical strategy for Stargate compute infrastructure across current and future generations. Evaluate CPU platforms across performance, efficiency, memory bandwidth, PCIe topology, cost, and roadmap alignment. Define storage architectures for AI environments, including boot media, local NVMe, shared storage, caching tiers, metadata services, and high-performance data pipelines. Drive server platform de

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Rack Power Engineer with deep expertise in high-power conversion and distribution to design, qualify, and support power systems for AI supercomputers. You will own rack power solutions—including power shelves, AC/DC rectifiers, power supply units (PSUs), power management controllers (PMCs), and high-current distribution—from requirements and supplier development through deployment. You will also monitor fleet rack power health, lead debugging and root-cause investigations, and drive improvements into hardware, firmware, and qualification coverage. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own rack power architecture and requirements for high-power AI supercomputing systems, including power budgets, AC input interfaces, DC distribution, redundancy, efficiency, serviceability, and integration with data center infrastructure. Drive the design and supplier development of power shelves, rectifiers, PSUs, PMCs, busbars, connectors, and protection circuits. Review electrical designs and control behavior, and evaluate performance, cost, reliability, and availability trade-offs. Define and execute component, shelf, and rack qualification plans covering load transients, current sharing, hot-swap, startup and shutdown, redundancy failover, fault protection and recovery, thermal limits, and AC disturbances and ride-through

About the Team DoorDash Labs, established in 2018, serves as the innovation hub for DoorDash, focusing on developing automation and robotics solutions to enhance last-mile logistics. The team's mission is to create technologies that support and augment human networks, aiming to improve efficiency for Dashers, merchants, and consumers alike. We’re ruthlessly focused on business impact. We are a highly senior team composed of former pioneers from a variety of different robotics industries. As of 2025, DoorDash has completed 10B lifetime deliveries. We’re focused on how to do the next 10B even better. About the Role We’re looking for a Senior/Staff electrical and firmware engineer who designs the board and writes the firmware for connected consumer and enterprise devices, including tablets, POS systems, peripherals, and emerging robotics applications. In this role, you will take connected devices from ambiguous user or business needs through system architecture, rapid prototyping, board design, firmware implementation, bring-up, field deployment, and production transition. The ideal candidate has a passion for building and shipping reliable hardware at scale and thrives in an environment that demands technical depth and high-quality execution across multiple concurrent programs. This is a build-heavy role on a small, senior team. You’re excited about this opportunity because you will… Own connected devices end to end, including: Own connected devices from an ambiguous product need through field deployment. Work across the hardware and firmware boundary instead of handing work between specialists. Explore uncertain product ideas through rapid prototypes and experiments. Make consequential tradeoffs on a small, senior team with direct exposure to users and field behavior. Key Responsibilities Translate user and business needs into an integrated electrical and firmware architecture. Design compute-based, mixed-signal boards incorporating processors

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators. You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality. In this role, you will: Develop, build and own tools, flows and methodologies for physical implementation Own physical implementation of floorplan blocks from floorplanning to final signoff Collaborate with RTL designers to drive optimal block implementation solutions Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners Qualifications: BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development Demonstrated success in taping out complex silicon designs Hands-on experience with block physical implementation and PPA convergence Strong coding experience with python, bazel, TCL Strong experience building physical design tools, flows and methodologies Strong understanding of microarchitecture, RTL design,

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a product manufacturing & quality engineer, who will be responsible for driving technical initiatives related to the manufacturing, quality and reliability of our AI supercomputer hardware systems to ensure product success from concept to launch and through mass production. You’ll have the opportunity to coordinate with functional SMEs and work with a wide range of stakeholders, from design engineering and operations teams, TPMs, external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees In this role, you will: Own the integrated manufacturing and quality readiness for a product across L6, L10, and L11, with clear gates, milestones, deliverables, owners, and closure criteria. Lead readiness of process flows, tooling, fixtures, assembly operations, test interfaces, and production controls. Review and contribute to work instructions. Translate product requirements into qualification plans, process controls, test requirements and acceptance criteria with design engineering and Area SMEs Coordinate and drive execution of product and process qualification, reliability testing, and validation with the relevant SMEs. Maintain traceable evidence that assigned products and processes meet agreed performance, reliability,

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a Product Manufacturing Engineer to drive manufacturing strategy and execution for next-generation AI hardware within the Silicon & Systems team, with a particular focus on PCBA manufacturing, assembly, process development, and production readiness. You will work closely with design engineering, systems engineering, operations, TPMs, contract manufacturers, suppliers, and other external partners to ensure new hardware products successfully transition from concept and prototype builds through NPI and high-volume production. You’ll own critical manufacturing initiatives, identify and resolve production risks, and help establish the processes and controls required to deliver complex hardware at scale. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Drive manufacturing and quality initiatives to ensure product success from concept and early development through NPI, production launch, and scale. Lead manufacturing process development for next-generation AI hardware systems, partnering closely with design engineering, systems engineering, operations, TPMs, suppliers, and manufacturing partners. Own PCBA manufacturing development and production readiness, including assembly processes, process validation, manufacturing test, rework, yield improvement, and successful transition into volume production. Establish NPI manufact

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development. Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability. Develop, validate, and apply package reliability models and lifetime-prediction

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As a Supply Chain Program Manager, you will own material readiness and supply chain execution for critical hardware programs spanning custom silicon, systems, memory, storage, networking, and rack infrastructure. You will work cross-functionally with Engineering, Strategic Sourcing, Manufacturing Operations, Finance, Planning, Quality, and external suppliers to develop and execute scalable supply strategies that support aggressive product development and deployment timelines. This role requires deep understanding of hardware supply chains, material planning, NPI execution, supplier management, and operational scaling in constrained and rapidly evolving environments. In this role you will: Material Readiness & Supply Planning - Own end-to-end material readiness across NPI and production phases, including building the necessary framework and processes for enablement. Drive supply planning and execution for long lead-time and constrained commodities including ASICs, HBM, DDR, SSDs, networking, optics, power, thermal, and mechanicals. Build and manage material readiness plans aligned to proto/pre-EVT, EVT, DVT, PVT, and mass production schedules. Monitor supply health, lead times, inventory positions, allocation risk, and capacity constraints. Drive shortage management, allocation mitigation, and recovery planning. Coordinate supply commits, forecast alignment, and supply continuity planning with suppliers and manufacturing partners. Cross-Functional Program Ma

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As a Hardware Chips Programs Manager at OpenAI, you will help bring our chips hardware roadmap to life, navigating an array of technical and partnership challenges. We’re looking for people excited to push the frontiers of computing by navigating technical explorations and are passionate about building. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Manage the design and implementation planning of our ML acceleration hardware, working across technical, cross-functional and external stakeholders Lead planning and scheduling of chip hardware designs with our strategic partners and vendors Coordinate and marshal internal resources and communication for efficient interaction with partners and vendors. You might thrive in this role if you: Have experience as a technical program manager for data center hardware products (server, GPU, TPU, networking, storage and so on) Know the whole end-to-end system program management from concept, design, production, deployment into the data center Have some experience with System SW programs through NPI Want to help design some of the world’s largest supercomputing systems, working at the edge of complex hardware challenges Enjoy working with and enabling world-class AI Researchers and Engineers Are passionate about the technical program function, and enjoy independently owning and delivering on your tea

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for a product manufacturing engineer, who will be responsible for driving technical initiatives related to manufacturing to ensure product success from concept to launch and through mass production with a specific focus on PCB and PCBa manufacturing and process. You’ll have the opportunity to work with a wide range of stakeholders, from design engineering and operations teams,TPMs, external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: In this role, you’ll be responsible for driving manufacturing and quality initiatives to ensure product success from concept to launch Lead the product design and the manufacturing process for next-gen AI hardware system development, you will have the opportunity to work with a wide range of stakeholders, from design engineering and operations teams, TPMs and external industry vendors and partners to ensure that all products are developed and delivered on time and to the highest quality standards. Lead the team to establish NPI product manufacturing process, systems and quality controls, defining clear milestones and deliverables, drive internal process improvements across multiple terms and functions Provide hands-on product manufacturing analysis during desi