Hbm Hardware Emulation Architect Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Architecture team defines the future of memory systems that enable next-generation AI, machine learning, and high-performance computing applications. By researching advanced memory architectures, system designs, and emerging technologies, the team develops innovative solutions that maximize performance, scalability, and efficiency for future memory products. As a Memory System Architect on the HBM Architecture team, you will contribute to the definition of future memory architectures supporting Generative AI and data-intensive workloads. You will research and evaluate advanced memory system concepts, analyze AI accelerator architectures, and develop models that guide product strategy and technology roadmaps for next-generation memory solutions. Responsibilities Research and evaluate advanced memory architecture concepts for AI accelerators, including GPU, TPU, and emerging compute platforms. Develop and analyze system-level models to assess performance, power, scalability, and efficiency across memory and compute architectures. Investigate memory hierarchy optimizations involving HBM, DRAM, cache, storage, and interconnect technologies. Evaluate architectural trade-offs and emerging technologies, including compute-near-memory concepts, to support future product development. Collaborate with cross-functional teams to translate research findings into architecture recommendations and long-term technology roadmaps.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron Technology, Inc., you will join a team responsible for bringing next-generation High Bandwidth Memory (HBM) products from design through high-volume manufacturing. This role plays a critical part in improving product reliability, accelerating production ramp, and enabling early time-to-market through advanced failure analysis. You will focus on analyzing failures from production test, internal qualification, and customer returns (RMA), using a combination of electrical, physical, and data-driven techniques to identify root causes related to fabrication or assembly processes. Key Responsibilities Perform electrical failure analysis and fault isolation using techniques such as emission microscopy, laser-based methods, and EOTPR. Analyze and model failure signatures from backend testing, qualification, and RMA data. Apply physical failure analysis (PFA) and de-processing techniques to isolate defects. Develop and maintain deep technical knowledge of CMOS/FinFET fabrication processes, device structures, and process integration. Generate clear, organized, and timely failure analysis reports, including root cause and corrective action insights. Collaborate multi-functionally with Product, Process, Assembly, Quality, and Management teams to communicate findings and drive resolution. Apply AI-assisted tools and workflows to analyze large datasets, identify failure patterns, and accelerate root-cause determination. Support flexible work sch

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets. In this role, y ou'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows. Responsibilities Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features. Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures. Develop, integra

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Job Description We are the HBM Design Architecture team within Micron’s HBM DRAM Engineering Group. We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. Our team thrives on deep technical collaboration, global partnerships, and solving problems that truly push memory technology forward! In this full‑time onsite role, you will provide critical technology support for the design and development of advanced HBM DRAM products. You will serve as a bridge between internal design teams, foundries, and technology development groups, helping translate advanced process capabilities into scalable, high‑performance architectures. Your work will directly impact performance, power efficiency, reliability, and long‑term HBM roadmap success. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. The responsibilities outlined below represent key areas of focus for this role and are intended to be illustrative rather than exhaustive. Candidates are expected to demonstrate relevant experience in at least three of the five focus areas outlined below. Job Responsibilities Foundry Interface and Technology Alignment Act as the primary technical interface between foundry partners and Micron design organizations. Drive closure of design-process gaps through collaborative engagement with foundry process teams. Influence foundry

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description We are the HBM Design Architecture team within Micron’s HBM DRAM Engineering Group. We work at the intersection of design, technology, and manufacturing to deliver next‑generation HBM solutions that power AI and ML workloads worldwide. Our team thrives on deep technical collaboration, global partnerships, and solving problems that truly push memory technology forward! In this full‑time onsite role, you will provide critical technology support for the design and development of advanced HBM DRAM products. You will serve as a bridge between internal design teams, foundries, and technology development groups, helping translate advanced process capabilities into scalable, high‑performance architectures. Your work will directly impact performance, power efficiency, reliability, and long‑term HBM roadmap success. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Job Description The responsibilities outlined below represent key areas of focus for this role and are intended to be illustrative rather than exhaustive. Candidates are expected to demonstrate proven experience in at least three of the five focus areas outlined below. Foundry Interface and Technology Alignment Act as the primary technical interface between foundry partners and Micron design organizations. Drive closure of design-process gaps through collaborative engagement with foundry process teams. Influence foundr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products. Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules. Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving Media Health Manufacturing and activities for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. You will lead a portfolio of Best-In-Class Next Generation HBM Product focused on the critical KPI’s Quality, Cost, Cycle Time and Scale. This include lead the manufacturing test flow development and validation, improve the device/stacked yield with most optimized extrinsic and intrinsic reliability through in depth circuit debug, test coverage optimization and strategy innovation, test time improvement for manufacturing flow and drive the DFT (design for test) strategy to stage new ideas to improve cost, cycle time and quality. You will also collaborate with cross functional team (Fab, Product Leads, Design, Technology Development, Design, Test Solution Engineering etc) with diverse expertise to achieve both strategic and tactical objectives and stay ahead on technology and product leadership. The future of HBM are exciting and dynamics. Micron is seeking experienced individuals that find technical challenges engaging and invigorating. Responsibilities: Optimized Test Coverage: T

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a key leader within High Bandwidth Memory (HBM) Product Engineering Media Health team, you will spearhead and develop a high performing team driving both intrinsic and extrinsic reliability test development and execution for Micron’s latest HBM products, both on DRAM and Interface die and a stacked product. Your responsibility is to drive extrinsic DPM reduction (Time 0 and Field DPM) and lead the intrinsic reliability charter, along with optimized Manufacturing Test Flow to meet critical KPI’s Quality, Cost and Cycle Time. You will be leading the team to characterize the products from reliability aspect, identify the reliability gaps, working on root cause and resolution of qual and RMA failures pertaining to defectivity and intrinsic reliability margin and drive fab process improvement driven by the qual failures. Additionally, your team will also be the key person in frontend process conversion, where you will work with Fab, TD, GQ teams to establish robust business process for process conversions to facilitate yield improvements, DPM and Cost Reduction. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. The future of HBM are exciting and dynamics. Micron is s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s Design Engineering team and help drive the future of memory innovation. This team develops groundbreaking digital, analog, and mixed-signal circuitry that powers advanced memory solutions. You will collaborate with global teams across design, verification, process, and product engineering to deliver high-quality, scalable technologies that transform how the world uses information. As a Memory Design Engineer specializing in HBM, you will contribute to the design, optimization, and validation of memory, logic, and analog circuits. You will partner closely with multi-functional engineering and manufacturing teams to support product development and ensure robust, efficient, and manufacturable solutions. Key Responsibilities Design, layout, and optimize memory, logic, and analog circuits for HBM products Perform parasitic modeling, validation, reticle experiments, and support tape-out revisions Complete layout processes including floor planning, placement, and routing Conduct circuit verification using industry-standard modeling and simulation tools Collaborate with multi-functional teams (design, verification, process, product engineering) to ensure manufacturability and product success Use AI supported design and simulation tools to enhance circuit modeling accuracy, improve design efficiency, and accelerate development cycles Minimum Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineerin

Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Reliability) — Fab 10A, Singapore. Apply via Workday.

Principal Engineer/MTS – Member of Technical Staff, HIG-HBM Product System Engineering (Media Health Manufacturing) — Fab 10A, Singapore. Apply via Workday.