Hbm Process Engineer Jobs

Staff Engineer, HBM Verification Architecture — Richardson, TX. Apply via Workday.

Principal Memory Design Engineer, HBM — Richardson, TX. Apply via Workday.

Engineer, HIG HBM, Product Engineering (Media Health Reliability) — Fab 10A, Singapore. Apply via Workday.

Sr Design Verification Engineer, HBM Verification Architecture — Richardson, TX. Apply via Workday.

Engineer, HIG-HBM Product System & Engineering (Media Health Manufacturing) — Fab 10A, Singapore. Apply via Workday.

Sr Design Engineer, HBM — Richardson, TX. Apply via Workday.

ENGINEER, High Bandwidth Memory (HBM) & New Product Introduction (NPI) — MSB, Singapore. Apply via Workday.

Sr Design Engineer, HBM — Richardson, TX. Apply via Workday.

Memory Design Engineer, HBM — Richardson, TX. Apply via Workday.

ENGINEER, PDE HBM NPI — Taichung - Fab 16, Taiwan. Apply via Workday.

Principal DFT Engineer, HBM — 2 Locations. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Architecture team defines the future of memory systems that enable next-generation AI, machine learning, and high-performance computing applications. By researching advanced memory architectures, system designs, and emerging technologies, the team develops innovative solutions that maximize performance, scalability, and efficiency for future memory products. As a Memory System Architect on the HBM Architecture team, you will contribute to the definition of future memory architectures supporting Generative AI and data-intensive workloads. You will research and evaluate advanced memory system concepts, analyze AI accelerator architectures, and develop models that guide product strategy and technology roadmaps for next-generation memory solutions. Responsibilities Research and evaluate advanced memory architecture concepts for AI accelerators, including GPU, TPU, and emerging compute platforms. Develop and analyze system-level models to assess performance, power, scalability, and efficiency across memory and compute architectures. Investigate memory hierarchy optimizations involving HBM, DRAM, cache, storage, and interconnect technologies. Evaluate architectural trade-offs and emerging technologies, including compute-near-memory concepts, to support future product development. Collaborate with cross-functional teams to translate research findings into architecture recommendations and long-term technology roadmaps.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As part of the Cloud Memory Business Unit (CMBU), this team advances Micron’s leadership in High Performance Memory solutions supporting Artificial Intelligence (AI), Machine Learning (ML), and High Performance Computing (HPC). The organization operates at the forefront of memory innovation, partnering closely with customers to enable next-generation computing capabilities. The Product Manager is responsible for defining and delivering the strategy for a High Performance Memory product portfolio. This role is critical to expanding Micron’s leadership in the HBM market by aligning product direction with customer needs, market trends, and emerging technologies, while driving cross-functional collaboration to deliver competitive solutions. Responsibilities Analyze emerging trends in AI hardware and evaluate their implications on high-performance memory architectures Define and drive product strategy and roadmap for high-performance memory products, ensuring alignment with market requirements and business goals Engage with customers, industry partners, and internal teams to gather insights on evolving AI/ML workloads and translate them into product requirements Assess the impact of next-generation AI workloads on future memory architectures and influence long-term product direction Support AI accelerator market analysis, including development of Total Addressable Market (TAM) and Serviceable Availab

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub