Hbm Shift Production Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Summary The DRAM Packaging organization is responsible for developing and delivering advanced memory packaging solutions that enable Micron’s next generation products. The team partners across design, technology development, manufacturing, quality, supply chain, and external ecosystem partners to drive innovation, accelerate product development, and deliver industry-leading packaging technologies that support markets including AI, cloud, mobile, automotive, high-performance computing, and data centers! Position Overview As the Director of DRAM Packaging, you will lead the strategy, development, and execution of advanced packaging solutions across Micron's memory portfolio. You will define technology roadmaps, drive innovation in next-generation packaging architectures, and build a high-performing global engineering organization. This executive leadership role combines technical expertise, business strategy, customer engagement, and digital transformation to accelerate innovation, improve organizational effectiveness, and strengthen Micron’s competitive position. Responsibilities Define and execute long-term DRAM packaging strategies that support future product, technology, and business objectives Lead development and deployment of advanced packaging technologies, including HBM, LPDRAM, DDR, 2.5D/3D integration, heterogeneous integration, chiplets, and next-generation interconnect solutions Drive adoption of AI, machine learning, advanced analytics, and digital engineering

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior Engineer, MCT Operations Quality at Micron Technology, Inc., you will lead and collaborate closely with Global Assembly & Test (AT) sites, Global Quality, and various cross-functional stakeholders to drive on Manual Touchpoint Reduction. You will champion a Quality-First mindset by driving manufacturing solutions and end-to-end redesign initiatives to eliminate manual steps upfront that reduce operational error, prevent customer events and enhance product quality across Global AT network. Job Responsibilities: Lead global initiatives and collaborate with AT sites and Global Quality to identify and eliminate high-risk manual touchpoints across Assembly, Test/Post E, Module/SSD, HBM/PWF areas. Conduct onsite validation of the manual touchpoints at the source, identify quality risks, and propose improvements to eliminate the touchpoints. Collaborate with subject matter experts and drive the development and deployment of scalable solutions through physical automation/robotics, system automation, and Predictive Quality & Generative AI-enabled solutions. Collaborate with subject matter experts on end-to-end redesign initiatives to eliminate manual touchpoints upfront. Lead as the central team program governance to drive strategy, alignment, and execution consistency across all AT sites. Drive the rapid replication and scaling of proven solutions across AT sites through structured deployment frameworks

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a HIG IE Engineer, your responsibilities encompass tactical execution and planning to support tactical pillar, CAPEX and OCAP budget management, material planning for wafer probe C1-C4 to Micron IQP, build Business Processes to enable wafer level activities. Also to work as a window for wafer PRIME, pWLR and DOE material acquisition, drive sample deliveries to execution for Wafer Reliability and IQP Reliability. You are also expected to understand procurement of items, inventory logistic management, audits, continual improvements, 6S housekeeping, and project management. It is a must for a HIG PSE IE Engineer to be familiar with Claude Code, AI apps and leveraging AI for work productivity and quality improvements. Responsibilities include, but are not limited to: Able to utilize Claude Code and AI apps in regular work. Proven creation of Claude Code apps (Advantageous with more than one creation) Have clear knowledge of HBM wafer probe operations starting from Assembly to post C4. Have clear knowledge of wafer material acquisition from FE processes. Liaison with NPO, SIC, NPI teams from F15 and OMT. Have knowledge in MES/MAM attributes, tagging of lots from AAA, DAA and NAA lots. Familiar with CBG setting to ensure engineering wafers are not mixed with MFG wafers. Able to track E2E DOEs requests from start to CRD/MAD. Work closely with requestors on process needs. Able to work as a team with fellow members in a safe, cohesive, and collabo

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior Engineer, MCT Operations Quality at Micron Technology, Inc., you will lead and collaborate closely with Global Assembly & Test (AT) sites, Global Quality, and various cross-functional stakeholders to drive on Manual Touchpoint Reduction. You will champion a Quality-First mindset by driving manufacturing solutions and end-to-end redesign initiatives to eliminate manual steps upfront that reduce operational error, prevent customer events and enhance product quality across Global AT network. Job Responsibilities: Lead global initiatives and collaborate with AT sites and Global Quality to identify and eliminate high-risk manual touchpoints across Assembly, Test/Post E, Module/SSD, HBM/PWF areas. Conduct onsite validation of the manual touchpoints at the source, identify quality risks, and propose improvements to eliminate the touchpoints. Collaborate with subject matter experts and drive the development and deployment of scalable solutions through physical automation/robotics, system automation, and Predictive Quality & Generative AI-enabled solutions. Collaborate with subject matter experts on end-to-end redesign initiatives to eliminate manual touchpoints upfront. Lead as the central team program governance to drive strategy, alignment, and execution consistency across all AT sites. Drive the rapid replication and scaling of proven solutions across AT sites through struct

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We're advancing some of the most important technologies in modern computing. Our memory solutions power AI, cloud, enterprise, mobile, and high-performance computing platforms around the world. The Memory Systems Architecture team explores complex technical challenges across the memory stack and turns them into practical product innovations, helping shape the future of memory technologies and industry standards. As a Technical Staff Member, you will provide systems-level architecture leadership for next-generation memory solutions. This role combines analytical modeling, architecture development, reliability strategy, and cross-functional influence to help define future products. You will work across engineering disciplines to evaluate tradeoffs, guide technical decisions, and develop differentiated solutions that deliver value to customers and platforms. Responsibilities: Define architectures for DDR, LPDDR, HBM, CXL-attached memory, and emerging memory technologies. Develop analytical and simulation-based models to evaluate performance, reliability, power, thermal, and cost tradeoffs. Drive architecture requirements across DRAM, packaging, modules, controllers, platforms, and system software. Lead technical studies, roadmap development, and architecture recommendations supported by quantitative analysis. Influence cross-functional teams, mentor engineers, and contribute to patents, publications, and standards activities. Mi

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron’s vision is to transform how the world uses information to enrich life for all . Join a world-class global team focused on one thing: using our expertise in the relentless pursuit of innovation to enable high value technology driven solutions for customers and partners. The solutions we create help make everything from virtual reality experiences to breakthroughs in supercomputing and artificial intelligence possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can spark the very innovation we are pursuing. We are currently experiencing a ground-breaking period in artificial intelligence (AI), where AI is anticipated to become an integral component of daily life. This proliferation is being fueled by advances in memory and compute technologies. High bandwidth memory (HBM) is at the forefront of these innovations. Micron’s Advanced Packaging Technology Development (APTD) is responsible to deliver package development for high performance memory products and transfer to manufacturing. Job Summary The Package Health Test Engineer will contribute to the development and execution of package health monitoring, simulation, and characterization activities. This role involves hands-on en

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Senior Engineer, MCT Operations Quality at Micron Technology, Inc., you will lead and collaborate closely with Global Assembly & Test (AT) sites, Global Quality, and various cross-functional stakeholders to drive on Manual Touchpoint Reduction. You will champion a Quality-First mindset by driving manufacturing solutions and end-to-end redesign initiatives to eliminate manual steps upfront that reduce operational error, prevent customer events and enhance product quality across Global AT network. Job Responsibilities: Lead global initiatives and collaborate with AT sites and Global Quality to identify and eliminate high-risk manual touchpoints across Assembly, Test/Post E, Module/SSD, HBM/PWF areas. Conduct onsite validation of the manual touchpoints at the source, identify quality risks, and propose improvements to eliminate the touchpoints. Collaborate with subject matter experts and drive the development and deployment of scalable solutions through physical automation/robotics, system automation, and Predictive Quality & Generative AI-enabled solutions. Collaborate with subject matter experts on end-to-end redesign initiatives to eliminate manual touchpoints upfront. Lead as the central team program governance to drive strategy, ali

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Business Development Manager for the Cloud Memory Business Unit (CMBU), you will help to drive the worldwide inbound and outbound marketing and business development activities for a key customer in the cloud computing / hyperscale space. You will define long-term strategy for the key account, influence internal and external product roadmaps, and champion customer-centric innovation to capture market share in this high-growth segment. In this position, you will analyze segment and marketing data, align existing products as well as document requirements for next generation products, and work with the cross-functional teams to develop and implement the strategy to enable Micron to continue to gain market share in this high growth and rapidly moving segment! The cloud product portfolio encompasses a comprehensive range of DDR, LPDDR and HBM based memory solutions supporting the requirements of our end market focus. Based on increasing growth opportunities across Cloud and AI, the structural definition, development, and delivery of a market leading Cloud strategy is a key imperative for CMBU and Micron! Responsibilities: Define and lead the account strategy to drive long‑term growth and profitability Strengthen our position as a trusted advisor across DDR, LPDDR, and HBM technologies Shape and deliver customer business and technical review strategies Advocate customer requirements within Micron product planning and roadmap processes

What We’re Looking For: We’re looking for an XPU Architect to own the XPU compute engine architecture of the A-0 and A-1 systems. This will initially involve heavily leveraging existing 3rd party IP, but in a creative way to solve the bandwidth demand challenges and memory system interface challenges. Future generations of the compute XPU will be semi-custom and custom designs. Ideal Background: An ideal candidate will have: Previous experience architecting and owning a high performance, high TDP ASIC (eg AI chips, network switch chips, high performance CPUs or similar) Knowledge of both computer architecture but also silicon implementation, and understanding of the realistic constraints that silicon implementation places upon architectural options Deep understanding of AI workloads, especially low latency LLM inference Understanding of workload and system level bottlenecks, especially around inference, as it pertains to interconnect, memory capacity, bandwidth, latency, etc. Strongly Preferred: Hands-on experience with AI chip architecture and tapeouts End to end ownership of at least one AI ASIC project History of product delivery (regardless of ultimate commercial success of said product) Experience with HBM-based AI chip architecture Experience in proposing “weird” chip architectures (in any domain, not just AI!)

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Customer Engineering team at Micron, where we partner directly with leading datacenter customers to solve complex challenges and bring cutting-edge memory solutions to life. Our work sits at the intersection of innovation and real-world impact—enabling faster computing, smarter systems, and breakthroughs across industries. This role is a key bridge between Micron and our customers. As a Datacenter DRAM Customer Engineer, you’ll act as a primary technical advisor, helping customers design, qualify, and deploy memory solutions that power next-generation compute platforms. You’ll collaborate across engineering, sales, and product teams while influencing both customer success and Micron’s product direction. Responsibilities: Drive design wins and product qualifications for DRAM, HBM, SSD, and compute-focused solutions Partner with sales and cross-functional teams to execute strategic customer plans and track progress Resolve system configuration, setup, and performance issues in customer environments Guide customers on memory architecture, system configuration, and optimization for cloud/datacenter workloads Support validation and deployment through lab activities, design reviews, and system-level testing utilize AI proficiency or AI‑enabled ways of working where applicable Minimum Qualifications: <s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron combines the brightest minds in the business with the world’s broadest memory portfolio of memory and storage technology, creating technology that leading global brands use to make computing faster, travel safer, healthcare more effective, and much more, addressing the world most challenging needs. Micron’s Customer Engineering Department plays a critical role in the company’s worldwide operations. With a career at Micron, you’ll be contributing your expertise to connect our customers with the industry’s most forward-thinking team to help reshape information, communication, and innovation around the globe. As an High Bandwidth Memory (HBM) Field Applications Engineer at Micron, you will be part of a high integrity, best-in-class customer engineering team ​responsible for strengthening technical partnerships, ​inspiring Micron and our customers to deliver ​the best possible products, and maximizing revenue​​. Responsibilities will include, but not limited to, the following: High Bandwidth Memory (HBM) Program alignment/expansion with key Micron customers, assist with Micron’s HBM qualifications, and Technical Opportunity management with our HBM customer engagements Extend/grow technical relationship with key HBM customers as the local execution and escalation point of contact Work with the Micron and customer qualification labs to complete qualification and debug any iss

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a SoC Architecture and Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the architecture, design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, design, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role for candidates passionate about architecture, RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Architect, design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Trans

About the Team OpenAI’s Hardware organization is building the infrastructure foundation for frontier AI systems. The Supply Chain organization is responsible for enabling scalable, resilient, and efficient supply chains across custom silicon, systems, networking, memory, storage, and rack-scale infrastructure. The Supply Chain Program Manager (SCPM) drives end-to-end material readiness and supply chain execution across the hardware lifecycle, from early architecture and sourcing strategy through production ramp and sustaining operations. We are looking for experienced supply chain leaders who can operate across technical, commercial, and operational domains to ensure material readiness, supply continuity, and execution excellence for complex AI hardware programs. About the Role As a Supply Chain Program Manager, you will own material readiness and supply chain execution for critical hardware programs spanning custom silicon, systems, memory, storage, networking, and rack infrastructure. You will work cross-functionally with Engineering, Strategic Sourcing, Manufacturing Operations, Finance, Planning, Quality, and external suppliers to develop and execute scalable supply strategies that support aggressive product development and deployment timelines. This role requires deep understanding of hardware supply chains, material planning, NPI execution, supplier management, and operational scaling in constrained and rapidly evolving environments. Responsibilities Material Readiness & Supply Planning - Own end-to-end material readiness across NPI and production phases, including building the necessary framework and processes for enablement. Drive supply planning and execution for long lead-time and constrained commodities including ASICs, HBM, DDR, SSDs, networking, optics, power, thermal, and mechanicals. Build and manage material readiness plans aligned to proto/pre-EVT, EVT, DVT, PVT, and mass production schedules. Monitor supply health, lead times, inventory positio

About the Team OpenAI’s Hardware organization develops system and infrastructure solutions optimized for advanced AI workloads. We collaborate across research, software, and external hardware partners to design and deploy next-generation AI systems at scale. Our team works closely with silicon vendors and system partners to evaluate emerging technologies, validate performance characteristics, and ensure that hardware capabilities translate effectively to real-world AI workloads. About the Role We are seeking a 3P Hardware Architecture Expert with deep expertise in GPU and accelerator architectures to engage directly with silicon vendors and guide hardware decisions for AI infrastructure. In this role, you will evaluate architectural tradeoffs across compute, memory, and interconnect systems, translating vendor specifications into real-world workload impact. You will play a critical role in early silicon evaluation, benchmarking, and performance validation, helping ensure that next-generation hardware meets the needs of our workloads. This role is highly hands-on and requires both deep technical understanding and the ability to engage at a high level with partners such as NVIDIA and AMD on architectural direction and design tradeoffs. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance. Key Responsibilities Engage deeply with silicon vendors (e.g NVIDIA & AMD) on GPU and accelerator architecture tradeoffs. Analyze and interpret performance, power, and efficiency characteristics of next-generation hardware. Translate vendor specifications into expected real-world performance for AI workloads. Evaluate architectural aspects including: compute throughput and utilization memory systems (HBM, cache hierarchies, bandwidth constraints) data types and precision tradeoffs (FP16, BF16, FP8, etc.) interconnect and scaling behavior. Run benchmarks and profiling to validate hardware performance a