High Speed Hardware Developer Jobs

About the Team DoorDash Labs is an independent team within DoorDash. We explore robotics and automation to transform last-mile logistics in the long term. If you have a passion for applying robotics solutions in a service used by millions of people, then we want to talk to you! About the Role As the Technician Lead, you will bridge the gap between high-level engineering goals and day-to-day shop floor execution. This is a "Player-Coach" role: you will spend 90-95% of your day as a hands-on contributor, executing high-level diagnostics and repairs alongside the team. You are responsible for ensuring the shift meets its daily output goals and uptime key results. While your primary focus is technical execution, you serve as the first point of escalation for the team and help ensure every technician is working efficiently and safely. You report to the Operations Manager, Service Operations, in our DoorDash Labs organization. This is an on-site role with expectations of 100% in-office work in the Bay Area, CA. This is across our locations in Fremont, San Jose, and Sunnyvale. You’re excited about this opportunity because you will… Lead the team to hit fleet uptime and repair goals while personally executing the most complex robotic diagnostics Perform advanced repairs, including component-level troubleshooting and fixes on intricate electrical systems, control units, and associated hardware, with minimal supervision Act as the process owner for the service center, creating and refining workflows that improve repair accuracy and shop efficiency Provide a high level of dependability and accuracy in all technical documentation and shift handovers, setting the "Gold Standard" for the technician team Lead medium-to-high complexity projects tied directly to fleet uptime and reliability key results from start to finish Serve as the primary DRI for troubleshooting systemic hardware issues and escalating critical bottlenecks to engineering Communicate clear success metrics for mai

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Accelerate Everpure’s AI momentum by transforming breakthrough infrastructure technology into high-impact digital experiences and technical narratives. In this strategic role, you will bridge modern AI frameworks and high-performance storage to define how enterprise technical leaders evaluate and adopt Everpure™ Data Stream Services, Portworx® by Everpure™, and our broader AI platform. By partnering closely with Product Management, Product Marketing, Solution Marketing, and Global Sales, you will establish the technical benchmark for AI data orchestration, converting complex architectures into clear market differentiation. WHAT YOU'LL DO Drive AI Technical Content & Campaign Strategy: Architect and deliver high-impact technical assets—including deep-dive technical guides, interactive demonstrations, and webcasts—that demonstrate how the Everpure™ Platform speeds AI/ML pipelines and RAG architectures. Build & Evangelize Hands-On Technical Showcases: Lead the strategy for interactive digital experiences on everpuredata.com, designing sandbox environments, TestDrive workflows, and live demonstrations for infrastructure architects and data engineers. Equip Field Teams with Technical Enablement: Own the technical enablement toolkit for global sales and partners, creating high-fidelity reference architectures, sizing frameworks, and competitive technical toolkits for major enterprise deals. Bridge Engineering Lo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview Our Munich engineering team develops mixed‑signal and IO solutions for next‑generation memory technologies. The group partners closely with global analog, digital, and product teams throughout the design and silicon lifecycle. Role Overview We are hiring an IO Design Architect to design new architecture, analysis, and validation of high‑speed memory IO. This role combines hands‑on circuit understanding with system‑level thinking and close collaboration across multiple design teams. Responsibilities Define and own the IO and PHY concepts for high‑speed memory interfaces Perform block‑level simulation, analysis, and feasibility checks Review and guide schematic‑level implementation to align with architectural intent Support verification, silicon bring ‑up, and debug activities Collaborate with

Principal Analog Design Engineer — Mixed-Signal PHY (Clocking / High-Speed I/O) — 2 Locations. Apply via Workday.

NVIDIA is a global leader in high-speed computer vision, artificial intelligence (AI), and deep learning. Our team develops data engineering solutions that empower AI developers in autonomous vehicle (AV) domains to innovate quickly and effectively at scale. Are you ready to take on a senior technical role in building high-performance AI data pipelines? We seek an exceptional individual to design and optimize microservices and data pipelines to process massive volumes of AV data and enable seamless data mining and AI training. The ideal candidate will bring expertise in big data processing and distributed computing to create efficient solutions and overarching architectures for challenges such as video data curation, behavioral search, and AI dataset management. What you'll be doing: Scope and build tools, microservices, workflows, and distributed applications to accelerate data mining and AI training. Design and implement solutions for streaming, resilience, logging, security, authentication, workflow orchestration, and data management. Deploy AI models. Design and develop Retrieval-Augmented Generation (RAG) workflows enabling hybrid and agentic patterns. Analyze and operationalize complex distributed systems for speed-of-light performance. What we need to see: Experience developing high-performance, scalable software systems. MS with 6+ years, or BS (or equivalent experience) with 8+ years of relevant experience in Computer Science, Computer Engineering, or a related technical field. Strong programming skills in Python or Golang Proficiency in key technologies like Kubernetes, Helm, Hive, Parquet, SQL, vector databases, e.g., Milvus. Strong architectural skills with a proactive, problem-solving mentality. Experience in data mi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. You will work on equalization and bandwidth extension to push the speed limits of the circuit and process technology, analyze resulting IO impairments, clock jitter and duty error impact to DRAM system and timing budget, and develop effective engineering solutions. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node. Minimum Qualifications: Minimum MSEE + 10 years or BSEE + 12 years of industry experience in analog and mixed-signal circuit design. Proficiency w

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Principal IO/Clocking Design Engineer to be a part of our design team working on critical high-speed circuits common to all DRAM related memory products! In this position, you will be responsible for the development, design, optimization, verification, and fan out of these high-speed circuits to all DRAM related projects at Micron. You will work on equalization and bandwidth extension to push the speed limits of the circuit and process technology, analyze resulting IO impairments, clock jitter and duty error impact to DRAM system and timing budget, and develop effective engineering solutions. Responsibilities: Innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products. Apply proven high-speed circuit design techniques and enhance critical performance evaluation of the IO data path and clocking path at circuit level. Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level. Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities. Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node. Minimum Qualifications: Minimum MSEE + 10 years or BSEE + 12 years of industry experience in analog and mixed-signal circuit design. Proficiency w

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a Signal Integrity Engineer to join our growing team. The ideal candidate will have a wealth of exposure designing high speed interconnects, breakout design, material trade-offs and verification. A background in electrical engineering, electronics or relevant fields is required. Must love all things high speed! This role is hybrid, based out of Santa Clara, CA or Austin, TX or Toronto, ON. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have a Bachelor’s degree in Electrical Engineering (or equivalent) and 5+ years working in high-speed digital design with a focus in high-speed PCB or package design at 10Gbps and above (e.g. 100GbE, GDDR6, PCIe Gen5+). You’re comfortable working with high-speed performance metrics such as ICR, ERL, COM, NEXT, and FEXT as well as knowledge of high-speed connector technologies, including NPO, CPO, and emerging standards. You are proficient with PCB ECAD tools (ideally Cadence Allegro). You communicate clearly (written and verbal), think critically, and love solving complex signal integrity problems. You’re enthusiastic about all things high speed and enjoy collaborating acro

NVIDIA is leading groundbreaking developments in Artificial Intelligence, High Performance Computing and Visualization. The GPU -- our invention -- serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables groundbreaking creativity and discovery, and powers inventions that were once considered science fiction, including artificial intelligence to autonomous cars. We are the GPU Communications Libraries and Networking team at NVIDIA. We build communication libraries like NCCL, NVSHMEM, and UCX that are crucial for scaling Deep Learning and HPC. We're seeking a Senior Software Architect to help co-design next-gen data center platforms and scalable communications software. DL and HPC applications have a huge compute demands and already run at scales of up to tens of thousands of GPUs. GPUs are connected with high-speed interconnects (e.g. NVLink, PCIe) within a node and with high-speed networking (e.g. InfiniBand, Ethernet) across nodes. Efficient and fast communication between GPUs directly impacts end-to-end application performance. This impact continues to grow with the increasing scale of next generation systems. This is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. Are you ready to build the new and innovative technologies that will help realize NVIDIA's vision? What you will be doing: Investigate opportunities to improve communication performance by identifying bottlenecks in today's systems. Design and implement new communication technologies to accelerate AI and HPC workloads. Explore innovative solutions in HW and SW for our next generation platforms as part of co-design efforts involving GPU, Networking, and SW architects. Build proofs-of-concept, conduct experiments,

We are excited to welcome a creative and independent Production Security Software Engineer for the IC test and product engineering group in NVIDIA Networking Business Unit. NVIDIA Networking Business Unit has continuously reinvented itself over two decades. Our high-speed buses & network products are leading in the markets with innovative ways to improve speed and bandwidth from one generation to another and today we are known as the go-to place for “End-to-End High-Speed Ethernet and InfiniBand Solutions”. We're looking to grow our company and build our teams with smart people who can join us at the cutting-edge technology. We are seeking a security engineer who will thrive in our innovative environment, who will help make our Network Silicon ICs products (Switch, NIC, SmartNic) secure. You will collaborate with test engineers, test house, Design, IT, vendors and many other professionals in the organization for the development of tools and test infrastructure for enabling security features in test and in all of our processes. At NVIDIA, we foster a collaborative and inclusive culture where your ideas can make an immediate impact. If you are passionate about enabling of the highest quality Network products in the market, we want to hear from you! What you'll be doing: Lead all security aspects in the integrated circuit production engineering team, including Define with security architects how to introduce new features into the ICPE production line Work with test engineers to add security related features into the test program, work with HSM vendors to provision our production lines with required security appliances an work with the production lines team to ensure smooth integration into the lines. Own the regression system to ensure no security related issues in the line, Enforce security reviews in internal SW development and work with corporate tools to ensure securi

NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. We are looking for a motivated Performance engineer to influence the roadmap of our communication libraries. The DL and HPC applications of today have a huge compute demand and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! This is an outstanding opportunity for someone with HPC and performance background to advance the state of the art in this space. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Conduct in-depth performance characterization and analysis on large multi-GPU and multi-node clusters. Study the interaction of our libraries with all HW (GPU, CPU, Networking) and SW components in the stack Evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available Triage and root-cause performance issues reported by our customers Collect a lot of performance data; build tools and infrastructure to visualize and analyze the information <li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Overview The Non-Volatile Engineering Group (NVEG) at Micron develops memory products that are best-in-class in die size, performance, reliability, and power! Our mission is to innovate and deliver groundbreaking non-volatile memory solutions such as NAND. As the pace of technology accelerates, NVEG is aggressively embedding AI across every stage of the design flow — from circuit exploration and layout optimization to silicon debug and specification analysis — and we are looking for engineers who not only use AI in their daily work but also actively reshape our engineering workflows to unlock AI’s full potential! Position Overview As a Principal Design Engineer in NVEG, you will architect, design and sign off the high-speed IO interface of next-generation NAND flash, moving data between the NAND die and the host controller at multi-GT/s rates under tight power, area and signal-integrity limits. You will own IO blocks end to end, from spec and architecture through circuit design, layout guidance, verification and silicon correlation. You will set IO architecture direction across products, lead task forces, and make the key trade-offs that hit aggressive data-rate and power targets. AI is a central pillar of how this team works: you will use AI tools daily and reshape wor

TERRITORY: Dallas West to Forth Worth East We are looking for a high-energy, adaptable, and results-driven Account Sales Representative (ASR) to join our Women’s Health sales team in the Dallas West territory! In this role, you will drive market adoption and business growth by supporting direct sales to OB/GYNs and Maternal-Fetal Medicine (MFM) specialists. The Dallas West territory is a fast-paced environment with high growth potential. You will work in lockstep with a fast-paced Clinical Field Specialist (CFS) partner. The ideal candidate isn't just a support player—they are a quick learner, a proactive go-getter, and a "sales chameleon" who can build immediate trust, match their CFS’s rapid pace, and help grow the territory. Primary Responsibilities Drive Growth in current sending accounts: Work directly with your assigned CFS to execute strategic territory plans, target growth in current sending accounts and maintain them. Partner at Pace: Work in seamless alignment with a high-speed CFS partner. Match their urgency, learn on the fly, and absorb administrative and customer support tasks so the team can close business faster. Adaptable Customer Engagement: Act as a true account chameleon—effortlessly tailoring your communication style, clinical knowledge, and interpersonal approach to connect with everyone from head physicians and practice managers to medical assistance and other staff. Account Logistics & Support: Assess the needs of medical professionals and staff members with a relentless focus on customer support, sample/logistics coordination, and rapid problem-solving. Maintain & Protect Existing Business: Ensure existing accounts receive white-glove service to maintain high retention rates while introducing currently marketed products and supporting new product launches. Cross-Functional Communication: Work closely with internal

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions. • Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams. • Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts. • Work with internal teams, customers, IP pr

We are now looking for a Senior SRAM Engineer within our Full Custom Memory (FCM) team! The FCM team designs specialized RAM implementations across NVIDIAs wide array of processing chips. Be it high speed, low power, multiport, we engage closely with processor architecture teams to build custom solutions across the entire NVIDIA silicon portfolio. Are you interested in designing circuits for the next generation of AI chips? Join a team of dedicated engineers developing the custom SRAM circuits that help power these chips. What you'll be doing: Design best-in-class SRAM circuits using state-of-the-art technology processes Optimize circuits for performance, area, and power Collaborate with mask designers to craft high quality and dense pitch-matched layout Verify functionality, electrical integrity, and robustness Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon What we need to see: BS/MS/PhD (or equivalent experience) in Electrical or Computer Engineering Minimum 12 years of circuit design experience Strong understanding of SRAM and memory design techniques and macro/block development Ways to stand out from the crowd: Self-motivation, attention to detail, clear data analysis and presentation skills Familiarity with industry tools such as Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers Background with developing and using various flows and methodologies, in