High Speed Hardware Developer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to ESD Architecture Leadership & Strategy Define and own ESD architecture and protection strategy for high-speed I/O portfolios including: HBM (High Bandwidth Memory) / DDR / LPDDR PHY I/Os PCIe, USB, Ethernet, MIPI, and proprietary interfaces Lead ESD–I/O co‑design trade‑off decisions, balancing: Aggressive ESD targets (HBM / CDM / MM).Ultra‑low capacitance and leakage requirements Eye margin , jitter , bandwidth , return loss, and impedance matching Drive architectural choices for: Snapback clamps, rail clamps, diode steering networks. Triggered and advanced ESD devices (technology‑dependent). Domain isolation and sequencing protection for sophisticated SoCs Advanced Circuit Design, Modeling & Signoff : Perform and guide ESD circuit design and analysis at block and full‑chip level. Establish simulation methodologies for: Transient ESD stress (TLP‑equivalent behavior). Dynamic clamp triggering and current handling. I/O performance impact (cap loading, ringing, overshoot/undershoot. Own ESD modeling correlation: Work with device/modeling teams on compact models (dynamic R, triggering, CV behavior). Drive correlation between SPICE simulations, TLP/VF‑TLP, and silicon results. Act as the final technical authority for ESD Design reviews and signoff. Silicon Debug, Reliability & Qualification Ownership : Lead silicon-l

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Staff Engineer in Micron’s High Bandwidth Memory (HBM) Component Validation team, you will contribute as Subject Matter Expert (SME) and contribute to define new standards on validation development for advanced HBM products and ensure stable, scalable validation testing infrastructure with zero code-related escapes across various test flows and high speed memory validation. You own optimizing test flows, and lead technical problem solving for next generation HBM products. You’ll drive validation development deliverables and mentor junior engineers. Why Join Us You’ll gain hands-on experience with cutting-edge HBM technologies and validation platforms, working alongside global experts. This role offers opportunities to learn advanced validation techniques, drive and deliver product readiness, technology solutions and innovations, and grow into technical leadership roles. Responsibilities: Test program development SME: Drive and develop and maintain test programs for HBM component validation Deliver timely test program releases aligned with validation milestones and drive code quality, reviews, and release best-practices Drive test time optimization and parallelism improvements Drive tes

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic. Drive timing closure at block, sub

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, subsystem, and full‑chip levels while partnering closely with register‑transfer level (RTL) d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Work on electrical and physical design of high-speed interfaces in packages. Work on electrical model extraction and validation of package interconnects with circuit design team and IP vendor to optimize silicon layout and package design. Electrical modeling, simulation and characterization of high-speed interfaces. Develop and execute test plans to validate package electrical models with measurements. Work with product engineering and system engineering for package correlation and validation in system environment. Driving innovation into the future Memory generations within a dynamic work environment. Translate engineering problems into scalable Artificial Intelligence and automation solutions Educational & Other Requirements: MTech in Electrical Engineering with strong emphasis in Electromagnetics, Microwave, Antenna Theory and RF Circuits. Required Familiarity with Ansys, Siemens or Cadence tools for frequency domain modeling, Frequency domain analysis and transient time domain analysis. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio

About Mach Industries Founded in 2023, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms. At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 350 employees, we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role Mach Industries is seeking a Test Instrumentation Engineer to own the external data capture architecture for flight tests across our autonomous UAS platforms. This role is responsible for the systems around the vehicle that tell us what actually happened during a test, including high-speed video, drone footage, external sensors, range instrumentation, and precise time synchronization between those sources and vehicle telemetry. This is a hands-on field engineering role for someone who can design, deploy, troubleshoot, and validate multi-source capture systems in dynamic range environments. You will support the full test lifecycle, including planning, readiness reviews, dry runs, day-of-test execution, and post-test data handoff. Because Mach develops low-cost, rapidly iterated UAS platforms, external instrumentation is often critical to failure analysis and engineering decision-making. In some cases, the external dataset becomes the most important record of the event. Success in this role requires technical judgment, discipline under field conditions, and the ability to turn raw test capture into trusted engineering evidence on a fast development cadence. Key Responsibilities Plan and deploy external data capture systems for flight tests, includ

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Signal Integrity (SI) Research & Development team enables the electrical performance of Micron's industry-leading memory and storage products, including DRAM, LPDRAM, NAND, HBM, SSDs, and emerging memory technologies. The team works across silicon, package, PCB, and system-level designs to develop high-speed signaling and power delivery solutions that support next-generation computing, AI, networking, automotive, mobile, and data center applications. As a Signal Integrity Engineer, you will support the design, analysis, and validation of high-speed memory interfaces and power distribution networks across Micron's product portfolio. Working alongside experienced engineers, you will use modeling, simulation, measurements, and AI-enabled workflows to evaluate signal and power integrity performance, support product development, and contribute to future technology and industry standards initiatives. Responsibilities Support signal integrity and power integrity analysis for high-speed memory interfaces and power distribution networks through modeling, simulation, measurement, and correlation activities. Collaborate with silicon, package, product, validation, and system engineering teams to ensure product electrical performance across all stages of development. Develop and evaluate die, package, PCB, and system-level models to identify performance risks and optimization opportunities. Apply AI-enabled tools and agentic workflows to improve engineering efficiency, automate analysis, improve

Job Details: Job Description: Join Intel's Silicon and Platform Engineering Group (SPE) as an Exempt Tech Contract Employee, The Role and Impact :As a Power Integrity Engineer, you will play a pivotal role in ensuring Intel's platforms and products meet the highest standards of performance and reliability. This position offers you the opportunity to work on cutting-edge technologies, designing and optimizing power delivery networks for complex high-speed platforms, boards, packages, and silicon. Your contributions will directly impact Intel's ability to deliver industry-leading solutions to its customers, driving innovation in power integrity and enhancing the performance and functionality of our silicon and systems. Join us to tackle exciting challenges and create impactful solutions that push technological boundaries. The primary responsibilities for this role will include, but are not limited to: Develop and analyze power delivery networks, including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards. Define power grid specifications and power and area targets to achieve optimal balance between power integrity and performance. Design test structures, electrical analysis methodologies, and verification plans to address power integrity challenges. Perform measurements to characterize power noise profiles across frequency, ground bounce, and other critical metrics, verifying power delivery networks post-design. Correlate measurements back to presilicon analysis and estimations for improved accuracy. Apply expertise in power integrity design and tradeoffs to guide simulations of power networks and physical implementations for packages and platforms. Ensure on-die power noise meets system-on-chip (SoC) functionality an

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Work on electrical and physical design of high-speed interfaces in packages. Work on electrical model extraction and validation of package interconnects with circuit design team and IP vendor to optimize silicon layout and package design. Electrical modeling, simulation and characterization of high-speed interfaces. Develop and execute test plans to validate package electrical models with measurements. Work with product engineering and system engineering for package correlation and validation in system environment. Driving innovation into the future Memory generations within a dynamic work environment. Translate engineering problems into scalable Artificial Intelligence and automation solutions Educational & Other Requirements: MTech in Electrical Engineering with strong emphasis in Electromagnetics, Microwave, Antenna Theory and RF Circuits. Required Familiarity with Ansys, Siemens or Cadence tools for frequency domain modeling, Frequency domain analysis and transient time domain analysis. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Lead full-chip floor planning, integration, physical implementation, signoff, and tape-out execution. Drive layout implementation of complex analog, mixed-signal, memory, and high-speed interface designs. Own DRC, LVS, ERC, EMIR, reliability, and manufacturability closure. Define and scale layout methodologies, best practices, and execution frameworks. Leverage Artificial Intelligence, Machine Learning, and Agentic AI to improve layout productivity, design quality, automation, and faster decision-making. Drive automation initiatives using AI-assisted design, verification, debugging, and knowledge management solutions. Lead cross-functional and global teams, mentor engineers, and drive technical excellence. Qualifications B. Tech /M. Tech in Electrical Engineering, Electronics, VLSI, or related field. 15&#43; years of hands-on custom layout experience. Proven success leading full-chip programs from concept through silicon tape-out. Deep expertise in: Analog & Mixed-Signal Layout Memory & High-Speed Interface Layout Full-Chip Floor planning & Integration Signal Integrity, Power Integrity, EM/IR Physical Verification & Signoff Advanced Node Technologies (FinFET/GAA) Strong proficiency with Cadence Virtuoso, Calibre, StarRC, Totem, and related EDA tools. Proven experience leveraging <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Own and drive custom analog and mixed-signal layout for critical LPDDR PHY blocks, including Datapath, bias networks, IO front ends, and reference circuits, ensuring robust operation across PVT, low noise coupling, and high matching accuracy 3-12 years of solid hands-on experience in custom analog and high-speed layout design, with proven expertise in implementing and delivering critical analog blocks and LPDDR/high-speed interfaces at advanced technology nodes Lead high-speed LPDDR (LPDDRx) interface layout execution , solving complex signal integrity challenges such as skew control, impedance matching, shielding, crosstalk mitigation, and jitter sensitivity in advanced nodes Architect and implement scalable array-based layout strategies for DQ/DQS byte lanes, CA lanes, and replica paths, ensuring strict symmetry, pitch matching, repeatability, and multi-channel scalability Drive integration of custom digital and mixed-signal blocks within the PHY (training logic, calibration engines, test/debug circuitry), ensuring optimal clocking, congestion management, and isolation from sensitive analog regions Lead layout-aware co-design with circuit teams , enabling early closure of timing, noise, IR, EM, and parasitic effects, and influencing design decisions from a layout perspective Establish robust power distribution, grounding, and isolation strategies , including guard rings, deep N-well usage, decoupling, and domain separation for

NVIDIA is now looking for a Senior Memory System Engineer to join our ASIC Memory Subsystem team! As a Senior Systems Engineer at NVIDIA, you'll join a group of hardworking engineers to develop and architect innovative Memory Solution for Tegra SoCs. In this position, you'll make a real impact in a multifaceted, technology-focused company. You will work with memory controller/PHY and Platform / System architect, Firmware, SI/PI, Memory suppliers to design and architect cutting edge, high speed and lower power memory technology for NVIDIA CPUs and SOCs. What You Will Be Doing: Analyze future DDR/LPDDR/HBM technologies to determine optimum performance, power, function and RAS in memory for Next generation SOC and Systems. Collaborate with ASIC Architects, Designers, Software and Firmware SW/FW teams to drive memory technology and associated requirements for memory controllers. Define Memory module, Package, and PCB layouts appropriate to the system workloads Debug and bring up memory evaluation / validation and failure issues on memory technology. Collaborate with DRAM suppliers and industry partners on to develop memory and memory related component technology. What We need to see: Bachelor's degree or master’s degree in Electrical Engineering, Computer Engineering (CE), or a related field (or equivalent experience) 10 years of proven track record in DRAM design, module design, or memory sub system design. Deep understanding and strong fundamental of memory design, features, ECC algorithm, SI and PI (Training algorithm) in DDR, LPDDR, and HBM. Strong understanding of memory sub system level interaction with Cache, Memory controller and PHY. Experience in the design, bring-up and validation for memory failure analysis Experience with Python, C/C

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The ASIC Logic Design Team plays a critical role in developing the custom silicon that powers Micron's industry-leading memory and storage solutions. Our team designs high-speed, high-performance ASICs and memory controller IP, collaborating closely with engineers across design, verification, validation, and product development to bring innovative technologies from concept to production. As a Digital Design Engineer Intern, you will work alongside experienced engineers to help design and develop next-generation ASIC solutions. This internship provides hands-on exposure to advanced semiconductor technologies and the complete ASIC development lifecycle, including digital, analog, and mixed-signal design. You will have the opportunity to contribute to meaningful projects while building technical expertise in a collaborative and innovative environment. What You Will Do Support the design and implementation of high-speed digital logic for tester ASICs and memory controller IP. Collaborate with cross-functional teams including Design Verification, Analog Design, Synthesis, Physical Design, and Lab Validation. Assist with integrating digital designs alongside custom analog circuitry and third-party IP solutions. Participate in design reviews and contribute to technical documentation. Present technical concepts and project updates to engineering teams. Explore and leverage AI-enabled design methodologies, including Generative AI and AI-assisted engineering workflows, t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment. You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies. You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also n

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Staff Verification Architect and shape modular, scalable verification solutions for next-generation HBM DRAM products across multiple customer platforms! You will be part of a highly multi-functional team of technical domain experts. You will collaborate closely with Design Engineering, Product Engineering, Business Units, and external customer teams to ensure our future HBM roadmap is successful. You will apply your thorough understanding of testbench architecture, custom and SoC verification methodologies, and 2.5D & 3D package integration to analyze bottlenecks and propose innovative solutions targeting scalability, quality, and verification cycle time. Responsibilities: Deliver high-quality, on-time verification plans and architecture collateral across IP-level and SoC-level verification, and develop turnkey solutions for future designs based on look-ahead information from customers and the architecture team Drive co-verification through direct customer interactions, and mentor early-career engineers to strengthen team capability and tech