Layout Designer Jobs

About Us: Samara Aerospace is revolutionizing satellite design by addressing the challenges of deploying and managing large satellite constellations. Our innovative Hummingbird spacecraft bus offers a modular and scalable platform that streamlines satellite production and deployment, significantly reducing launch costs. Hummingbird's compact architecture maximizes launch capacity, making it the most efficient and agile spacecraft in the industry. At the core of our technology is the patented Multifunctional Structures for Attitude Control (MSAC) system. Unlike traditional wheel-based pointing control systems, MSAC utilizes actuators embedded in the hinges of deployable solar panels to provide 3-axis attitude control and active jitter cancellation. This design eliminates the need for spinning wheels, reducing mass and potential points of failure, while enhancing pointing precision. Role: The Electrical Engineering team at Samara is seeking an Electrical Engineer to lead the design, layout, and testing of printed circuit boards for spacecraft electronics at our headquarters in San Francisco. This is a startup environment where you will own designs end-to-end, from early concept through production. A strong problem-solving background, hands-on testing skills, and experience with high-density PCB design and electronics integration. You'll work closely with experienced electrical, mechanical, and embedded software engineers to ensure the Hummingbird satellite's electronics are robust, manufacturable, and ready for the space environment. Responsibilities: Own PCB Design from circuit design, schematic capture, and PCB layout through bring up testing. Conduct trade studies that balance electrical performance, signal integrity, thermal management, manufacturability, cost, and schedule. Collaborate with embedded software engineers during board bring-up, debugging, and hardware-software integration. Support spacecraft and board-level integration, including hands-on assi

The objective of the job is to handle project co-ordination with different EPCM- contractors, resolve technical queries, as per project specifications. Plan and track deliverables as per project planning. Knowledge of plant layout and piping concepts of stress analysis, optimize layout, contribute during model reviews, understanding of codes and standards, skill set of 3D-Model. Source: Adani Group | Job ID: 41654

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

... Address: No. 35 20th Main 1st cross BTM 1 stage next to Union Bank of India BTM layout Bangalore Facility: MOJO (Christ College Hostels) - FS Qualification: 12th Experience: 2 - 3 years Source: Sodexo India | Job Code: IJP565715

Position Summary : TaylorMade Golf China is launching the Application on mobile device to start eCommerce in China. This Application Operation Manager will be one of the members to involve in this project and be responsible the full cycle of eCommerce application from go-live to daily operation. Essential Functions and Key Responsibilities: Responsible for coordinating the overall operation plan of TaylorMade Golf China App (include but not limited: internal layout and optimization, column structure and channel, product functions and UI design, etc.), and responsible for implementation and execution Responsible for the development of APP content operation rules and content planning, and the daily data of APP platform, including content, traffic, click-through rate and conversion rate, etc., to work out formation of reports and provide proposal of improvement strategies Optimize the business process and product experience to improve user activity and retention according to APP operation objectives and user feedback Responsible for the overall UI design specification of APP client, control the visual effect, interactive experience, and graphic design (startup page, guide page, function page, etc.) Promote the brand awareness of the APP platform market through online and offline operation activities, enhance customer activity and transaction stickiness, and promote the performance of the APP platform Effectively and timely communicate design requirements with internal sales team, marketing team and product team Education, Work Experience, and Professional Certifications: Bachelor degree or above in related major, fluent in business English 5 years or above working experience in da

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Additional responsibilities include, but are not limited to: Responsibilities: Performs electrical or mechanical troubleshooting to determine problems in non-functioning electro-mechanical equipment used in the manufacturing process Dismantles, adjusts, repairs and assembles equipment according to layout plans, blueprints, operating or repair manuals, rough sketches or drawings Uses test and diagnostic equipment to perform checkouts. Rebuilds manufacturing equipment as required May perform equipment modifications as directed by engineers. Successful Candidates must have the following Qualifications: Knowledge of AC/DC circuits, including: fundamentals of electricity, and basic electronic components and circuits Strong mechanical aptitude with the ability to understand and fix mechanical systems Vacuum system knowledge and troubleshooting ability Ability to use schematic diagrams to troubleshoot systems to components level Intermediate PC skills including a familiarity with MS Office Suite. Understanding of the process flow related to area equipment Problem-solving skills and the ability to efficiently prioritize tasks Ability in multi-tasking complex projects and enjoy working in a fast pace environment Time management, organization, and prioritization skills Follows procedures and work with minimal supervision</li

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. ASIC IP STA Engineer (6-10 Years) | DDR PHY / ONFI PHY / IO Expander Location: Bengaluru, India Experience: 6-10 Years Enducational Qualification : BE/B-Tech/M-Tech (EEE, ECE, Micron Electronics, VLSI) Key Requirements Member of the AMS IP Physical Design team , responsible for post-layout STA signoff and timing closure of high-speed interface IPs, with close collaboration across IP Design, SoC Synthesis, and SoC Physical Design teams throughout IP development and SoC integration. 6-10 years of experience in Static Timing Analysis (STA) with a proven track record of 4 &#43; successful tapeouts . Strong hands-on expertise with Cadence Tempus (preferred). In-depth experience in MMMC timing analysis and closure across functional, scan, MBIST, and other DFT modes. Experience working on high-speed Memory Interface IPs such as DDR PHY, ONFI PHY, IO Expander (IOE) , or similar high-performance interface designs. Strong understanding of timing constraints development, validation, and debug , including clocks, generated clocks, timing exceptions, and mode-specific constraints. Experience in Liberty (.lib) and ETM timing model generation, validation, correlation, and quality assessment . <span

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

Job Details: Job Description: The Role and Impact As a GPU Platform Hardware Design Engineer, you will play a pivotal role in designing and developing high-quality GPU hardware platforms that drive innovation in high-performance computing, graphics, and visualization technologies. You will lead the design process from initial feasibility studies through board layout, tapeout, and platform power-on, ensuring robust functionality and compatibility with industry standards. Your expertise in platform-level requirements, electrical engineering applications, and system bring-up will directly contribute to delivering cutting-edge GPU systems that accelerate Intel's leadership in computing. Business group The Data Center Group (DCG) is dedicated to advancing Intel's role in powering the digital world with leading-edge technologies. Focused on delivering innovative solutions for data center and cloud environments, DCG supports high-performance computing and graphics to enable capabilities such as AI, machine learning, and advanced visualizations. As part of the GPU IP Engineering team within DCG, you'll contribute to developing GPU systems that meet the evolving demands of the industry while supporting Intel's broader mission to create world-changing technology. Key Responsibilities - Design, develop, and evaluate electronic components, PCBs, and integrated circuits for GPU hardware platforms. - Translate platform-level requirements into detailed specifications and ensure adherence throughout the design process. - Define component placement and trace routing rules to optimize board layouts for performance, power, and signal integrity. - Conduct feasibility studies, board layout, tapeout, and platform power-on activities. - Perform functionality tests and utilize tools to verify platform configurations and compatibility. - Research, develop, and validate firmware, hardwa

Job Details: Job Description: Join Intel's Advanced Packaging Technology Development - Substrate and Wafer Assembly (ATPD: SWA) team and help us fulfill our mission to be the supplier of choice for leading-edge, cost-effective substrate packaging. As a Manufacturing Equipment Technician, you will support critical manufacturing equipment and drive continuous improvement in a highly technical, cleanroom production environment. Shift 5: Shift 5: (days frontend) AM-PM Sun-Tues and alternating Wednesday days / Hours: 6:00 a.m.-6:00 p.m. Manufacturing Equipment Technicians in Advanced Packaging Technology Development: Substrate and Wafer Assembly are responsible for: Performing electrical and/or mechanical troubleshooting to diagnose issues with non-functioning electromechanical equipment used in semiconductor manufacturing. Dismantling, adjusting, repairing, and assembling equipment according to layout plans, blueprints, operating or repair manuals, rough sketches, or engineering drawings. Performing setup, calibration, and preventive maintenance on production equipment, with a focus on wet chemistry, plating, and dry high-vacuum toolsets. Documenting maintenance activities, repairs, parts usage, and findings in accordance with established procedures and systems. Collaborating with engineering, process, and support teams to improve tool performance, reduce equipment downtime, and enhance process capability and reliability. Leading or contributing to continuous improvement projects, including root cause analysis, yield and uptime improvement initiatives, and optimization of maintenance practices. Assignments are semi-routine in nature and performed within generally defined parameters. Employees normally receive general instructions on most work and are expected to exer

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Design Technology Package Co-Optimization (DTPCO) organization is seeking a Staff Engineer! Lead the design and development of test vehicles that enable technology learning and risk reduction for future HBM products! This role serves as a key technical contributor within DTPCO, partnering closely with Architecture, Design, Layout, Product Engineering, Reliability, and Advanced Packaging teams to translate emerging product requirements and technology challenges into actionable test vehicle solutions. You will apply expertise in semiconductor design, physical implementation, silicon characterization, and advanced packaging technologies to define test structures, develop validation strategies, and generate data that drives product decisions across future HBM generations. Unlike a traditional product role centered on ownership of product blocks, this position emphasizes enabling learning in development and engineering. It does so by developing representative test vehicles and characterization structures. Key Responsibilities Serve as a technical lead for HBM test vehicle design and structure development within DTPCO. Partner with HBM product, technology and reliability team. Define and implement test structures targeting key learning areas such as package interaction and reliability Drive test vehicle content definition, structure specifications, measurement requirements, and validation objectives. Analyze silicon characterization and qualification results to identify optimization opportunit

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Within Infrastructure Management Team the candidate is acting as single point of contacts for all business requirements linked to the Cloud. He/she is responsible for understanding current and future customer demand for services. He is preparing the CAB (change advisory board) The candidate must have significant experience in Cloud / SAAS / PAAS / Infrastructure / system integration/migration. Address: No.110/1 M Krishnappa Layout Lalbagh Road Facility: SBS IS&T Global SA SA Qualification: Graduate Experience: 10 - 15 years Source: Sodexo India | Job Code: IJP561563

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor