Layout Designer Jobs

ENGINEER - Planning (Layout) — Fab 10N/X, Singapore. Apply via Workday.

Engineer/ Sr Memory Layout Engineer-DPG-LPDDR — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Sr Engineer/Layout Engineer, Memory CAD, Guadalajara — Jalisco, Mexico. Apply via Workday.

STAFF ENG-HIG-HBM-LAYOUT — Jalisco, Mexico. Apply via Workday.

STAFF ENG-HIG-HBM-LAYOUT — Jalisco, Mexico. Apply via Workday.

Sr Engineer/layout Engineer, Memory CAD, Guadalajara — Jalisco, Mexico. Apply via Workday.

SENIOR ENGINEER HBM LAYOUT — Jalisco, Mexico. Apply via Workday.

PRINCIPAL ENGINEER HBM LAYOUT — Jalisco, Mexico. Apply via Workday.

Atom CPU Layout Design Engineer — Mexico, Guadalajara. Apply via Workday.

Atom CPU Layout Design Engineer — Mexico, Guadalajara. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Guide developing team members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI tools Qualification/Requirements 5 to 8-year experience in analog/custom layout design in advanced CMOS process. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of cr

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities: Optimize production equipment layouts by applying industrial engineering principles to improve material flow, footprint efficiency, and overall factory output. Maintain accurate and up‑to‑date layout documentation, ensuring that all planned tool installations, relocations, upgrades, and removals are reflected in the ramp‑plan layout. Perform onsite assessments together with Facilities and tool owners to validate layout feasibility, verify physical and infrastructure constraints, and ensure that proposed layouts accurately reflect operational conditions Collaborate closely with Manufacturing, Engineering, and Facilities to communicate layout changes, resolve constraints, and ensure alignment throughout the planning and execution process. Develop foundational understanding of fab design, cleanroom protocols, and process areas to support effective layout planning and operational readiness. Integrates AI-assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements. Contributes to a culture of continuous improvement by identifying, testing, and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role and Responsibilities Responsible for layout design and development of critical analog, mixed-signal, custom digital block, standard cells and full chip level. Perform layout verification like LVS, DRC, Antenna, Shield, Matching, Latch up, EM IR Totem checks, quality check and documentation. Responsible for development of digital block layouts using auto placement and route tools Responsible for basic understanding of skill coding and automation Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/achievements in multiple project environment. Guide developing team members in their execution of Sub block-level layouts & review their work Contribute to effective project-management. Effectively communicating with Global engineering teams to assure the success of layout project. Responsible for the reducing the layout effort by using AI tools Qualification/Requirements 5 to 8-year experience in analog/custom layout design in advanced CMOS process. Expertise in Cadence VLE/VXL and Mentor Graphic Calibre DRC/LVS is a must. Should have hands on experience in creating layout of cr

STAFF ENG-HBM-LAYOUT — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Design layout for leaf cells, standard cells (Stdcell), or sub-blocks. Apply a systematic, meticulous, and methodical approach to IC layout design. Interpret DRC/LVS and other physical verification checks to ensure design accuracy. Demonstrate ownership and proactively plan work to meet project timelines. Collaborate effectively with internal teams to ensure successful layout project execution. Minimum Qualifications Bachelor’s, Master’s, or PhD in Electronics, Mechatronics, Robotics Engineering, Nanotechnology, or related fields. Graduation within the last 2 years (Bachelor’s, Master’s, or PhD). Strong knowledge of electronic circuit concepts. Experience using circuit simulation and design tools. Effective interpersonal and problem-solving skills. English communication skills (conversational level required). Self-motivated, enthusiastic, and collaborative standout colleague. Passion for technology and willingness to grow in the semiconductor industry. Preferred Qualifications Internship or academic project experience in pre-silicon circuit design. Understanding of pre-silicon development areas such as analog circuits and physical design. Basic knowledge of MOS concepts, semiconductor fabrication, and analog layout fundamentals. Strong interpersonal skills and goal-oriented perspective. Experience with programming or script