Manufacturing Co Op Jobs

Careers that change lives start here. Medtronic is a global leader in healthcare technology with a Mission to alleviate pain, restore health, and extend life. Our 95,000 employees work across more than 150 countries to put patients first — developing innovative medical technologies that improve the lives of 72+ million patients each year. Your unique talents will help shape the future of healthcare while building a career grounded in purpose, growth, and impact. A Day in the Life The Villalba Manufacturing site manufactures medical technologies that support patients worldwide through advanced manufacturing processes and continuous improvement initiatives. The Manufacturing Engineering function partners closely with Operations, Quality, Research & Development, and Supply Chain teams to develop, optimize, validate, and sustain robust manufacturing processes that support safety, quality, delivery, and cost objectives. This position is based on site in Villalba, Puerto Rico, requiring close collaboration with manufacturing operations and cross-functional teams. The role serves as a technical leader for laser-based manufacturing technologies, process development, equipment implementation, and operational excellence initiatives to support supplier visits, training, benchmarking activities, and global project collaboration. Job Description field The Principal Manufacturing Engineer provides technical leadership for the development, implementation, optimization, and sustainment of manufacturing processes with a focus on laser technologies. This role leads complex engineering initiatives, supports advanced manufacturing solutions, and drives process performance, co

JOB DESCRIPTION: Program Highlights Abbott’s 3-year accelerated development program that builds broad Operations experience through three rotational assignments. Upon completing the program, OPDP members transition into full-time roles and continue building their careers at Abbott, leveraging the skills, experience, and network gained through the program. Program Overview Over the course of the 3-year program, OPDP members complete three key developmental experiences designed to accelerate learning and career growth. PDP members rotate through three assignments across different divisions or functional areas, including Technical, Supervisory, and Operations Excellence roles. Rotation opportunities may include Engineering, Materials Management, Project Management, Plant Quality and Operational Excellence, providing broad exposure to manufacturing and operations. Program Rotation Model Three 12-month assignments across different divisions and/or functional areas. Gain diverse experiences with each assignment led by a different Assignment Manager. Complete the program with an international assignment in the final year, graduating the program in June 2030 for those starting in July 2027. Requirement Bachelor’s degree/master’s in engineering or related disciplines (Only for graduates of 2025 to 2027 only) Interest in pursuing a career in Operations – Engineering, Manufacturing Production, Plant Quality, Supply Chain, etc. Track record of outstanding academic performance and co-curricular activiti

Define the physical limits of what a chip can do, then break them! NVIDIA's Silicon Co-Design Group sits at the crossroads of architecture, silicon, systems, and manufacturing, where first principles thinking translates directly into product outcomes at scale. As GPU power density and thermal limits approach physical boundaries, the gap between system architecture needs and manufacturable, testable capabilities widens with every generation, and this role exists to close it. You wouldn't be maintaining existing solutions, you'd be identifying where physical constraints will erode NVIDIA's competitive edge before anyone else sees it coming, then building the cross-domain responses that ensure the next generation leapfrogs those limits entirely. The problems here don't have known answers yet: Every generation of NVIDIA silicon pushes closer to the limits of physics. The Co-Design Architect role isn't about optimizing within known bounds; it's about redrawing those bounds entirely. If you want your work to shape what's physically possible in the world's most demanding computing products, this is where that work happens. What you'll be doing: Power, Thermal & Packaging Limits Analysis: Gather and analyze the hard constraints of packaging, power delivery, and thermal dissipation against roadmap demands, predicting when those constraints will reduce competitiveness and acting before they do. Cross-Domain Solution Development: Develop solutions that span silicon features, packaging innovation, firmware and hardware co-design, and DFX updates, ensuring future products are not only performant but testable to the highest quality and reliability standards. Packaging Technology Evaluation: Assess emerging packaging technologies for their voltage/frequency, noise, reliability, and testability implications, determining which are worth adopting an

About the team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the role: We are seeking an experienced Optical Network Engineer to lead Laser related work within our optical interconnect efforts for large-scale compute systems. The role also requires broad, hands-on optical validation experience across IM/DD-based interconnects, working from lab characterization through production readiness and scaled deployment. In this role you will: Drive laser-focused requirements and technical direction within the broader optical interconnect roadmap. Lead evaluation and validation of optical components and subsystems, including laser-based elements, in lab and production-representative environments. Support end-to-end optical testing for IM/DD interconnects (e.g., module/system bring-up, characterization, debug, and readiness for scale). Work with external partners to align on development milestones, performance targets, and quality expectations. Own technical issue triage and resolution across performance, reliability, and manufacturability topics. Collaborate across internal teams to support integration, rollout, and operational success at scale. You might thrive in this role if you have: Strong experience in laser-focused optical engineering (development, validation, manufacturing readiness, or field support). Broad hands-on background with IM/DD optical technologies and optical test/debug workflows. Experience working with external suppliers/manufacturing partners and production-oriented execution. Demonstrated ability to debug complex t

We are looking for a Junior Inside Sales Co-Ordinator in a pharma company who supports sales force by processing orders, managing field force documentation, preparing MIS sales reports, and tracking inventory . They act as a liaison between sales, manufacturing / supply chain, and customers to ensure smooth order execution . Key Responsibilities :- 1.) Providing support to the sales team for proposal building 2.) Cold calling prospective clients to initiate sales opportunities 3.) Handling the quotations proposals, and payments 4.) Handling customer queries as per the product information required, submitting quotations & follow ups 5.) Co-ordination with field engineers and customers Skills & Software Knowledge:- 1.)Freshers or Experienced both are welcome 2.)Good written and verbal communication skills 3.)Strong organizational skills and the ability to prioritize work 4.) Sound knowledge of ERP software & Excel Job Title :- Junior Inside Sales Co-Ordinator Location :- Goregaon East Job Type :- Full Time Salary :- 15000 - 22000 Experience :- 1-2 years

SLSQ227R148 As Partner Sales Director for Manufacturing & Energy, you own the partner go-to-market strategy for the vertical — architecting joint solutions with our most strategic partners, building durable pipeline, and holding partners accountable to execution that converts to partner-sourced and partner-influenced consumption. This is a highly visible, strategic role: you set the agenda across Sales, Field Engineering, Marketing, Partner Solution Architecture, and the partner ecosystem, and you carry Databricks' Manufacturing & Energy partner narrative to senior partner and customer executives. You will own and grow relationships with strategic partners across the vertical — including global and regional systems integrators such as Accenture, Deloitte, Capgemini, and IBM, and specialist data and AI partners — and you bring deep industry knowledge and an operator's mindset powered by modern AI tooling. Reporting to the Senior Director, Partner Sales. The impact you will have: Build and own the pipeline engine — architect the Manufacturing & Energy partner GTM strategy and convert it into durable, partner-sourced and partner-influenced pipeline and consumption across the vertical. Drive partner execution and accountability — hold strategic SI/ISV partners to joint commitments; inspect co-sell motions rigorously and remove friction so partners execute effectively against shared pipeline and revenue goals. Lead solution development with partners — co-create differentiated, industry-specific joint solutions, accelerators, and repeatable GTM plays that pair partner capability with the Databricks platform to solve high-value Manufacturing & Energy use cases. Run a disciplined operating cadence — pipeline reviews, forecast, and KPI inspection anchored to Salesforce as the system of record; report impact, not activity. Own the executive relationship and narrative — build joint business plans and executive-ready narratives, and represent Databricks credibly

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Engineer and Member of the Technical Staff in the Procurement and Operations Central Teams (PROCT) and Advanced Development Team (ADT), you will primarily focus in the early maturity phase of new products as they transition from technology development centers to our high-volume manufacturing sites. Your contributions to our team will support innovation and enable improvements in product yield, quality and cost reduction that are vital to enable our manufacturing strategy. We are looking for outstanding candidates experienced with semiconductor process development/optimization, hardware and supplier management, and an understanding of NAND & DRAM integration to contribute and grow with our organization. Good organization skills and the ability to work independently or in teams is a must and because this role is essential to the success of Micron's products it will require international travel to Micron manufacturing and technology development sites. Your responsibilities include, but are not limited to: Collaborate with Technology Development (TD) on future technology requirements and model of record requirements to ensure manufacturing roadmap is aligned with the forward technology path Partner with TD and Manufacturing on supplier engagement to ensure resources meet Micron's strategic objectives. Collaborate with Manufacturing as new products are introduced to improve performance and enable customer qualification. Connect with co

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Engineer and Member of the Technical Staff in the Procurement and Operations Central Teams (PROCT) and Advanced Development Team (ADT), you will primarily focus in the early maturity phase of new products as they transition from technology development centers to our high-volume manufacturing sites. Your contributions to our team will support innovation and enable improvements in product yield, quality and cost reduction that are vital to enable our manufacturing strategy. We are looking for outstanding candidates experienced with semiconductor process development/optimization, hardware and supplier management, and an understanding of NAND & DRAM integration to contribute and grow with our organization. Good organization skills and the ability to work independently or in teams is a must and because this role is essential to the success of Micron's products it will require international travel to Micron manufacturing and technology development sites. Your responsibilities include, but are not limited to: Collaborate with Technology Development (TD) on future technology requirements and model of record requirements to ensure manufacturing roadmap is aligned with the forward technology path Partner with TD and Manufacturing on supplier engagement to ensure resources meet Micron's strategic objectives. Collaborate with Manufacturing as new products are introduced to improve performance and enable customer qualification. Connect with co

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Join Micron’s SSD Hardware Engineering team and help shape the next generation of storage solutions that power data centers, AI infrastructure, client computing, and intelligent edge applications. We are passionate about delivering innovative memory and storage technologies that transform how the world uses information to enrich life for all. Our team works across hardware, firmware, validation, manufacturing, and system engineering to bring industry-leading SSD products to market. As an SSD Hardware Engineer, you will play a key role in the development of next-generation SSD products from concept through production. This is an outstanding opportunity to influence system architecture. You will solve sophisticated high-speed build challenges and drive product quality, performance, and reliability. You will also work with emerging AI-enabled engineering platforms and mechanization technologies. Responsibilities: Lead SSD hardware development activities across the product lifecycle, including design, validation, characterization, and production support Collaborate with technical teams with varied strengths to define requirements, review architectures, and deliver hardware solutions that meet performance, quality, and manufacturability goals Perform signal integrity and power integrity analysis, simulation, validation, and debugging for high-speed interfaces and subsystems Drive board bring-up, hardware debugging, root cause analysis, and technical inve

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking a Package Reliability Engineer to lead reliability engineering for advanced packages used in high-performance AI and computing systems. The primary focus of this role is to assess package level mechanical and thermal reliability risks and apply thermal and mechanical modeling to optimize package design, material selection, and assembly processes. The engineer will also develop reliability test plans with external partners, identify failure mechanisms, perform root-cause analysis, and recommend practical corrective actions. In this role, you will assess package reliability risks from early architecture development through product qualification and high-volume manufacturing. You will work closely with package design, silicon design, system engineering, manufacturing, and ASIC partners to predict package behavior, develop qualification strategies, resolve reliability issues, and improve overall package robustness and lifetime. In this role you will: Lead reliability test plan and assessments for advanced HPC packages, including risk identification, potential failure-mechanism analysis, root-cause investigation, mitigation planning, and corrective-action development. Drive reliability-focused package design optimization based on thermo-mechanical modeling to improve package reliability, power integrity, thermal performance, mechanical robustness, and platform scalability. Develop, validate, and apply package reliability models and lifetime-prediction

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a Security Engineer to join our First-Party Hardware team. In this role, you will own the end-to-end security foundation for OpenAI's first-party AI hardware systems, working across hardware security, embedded security, system security, and practical deployment at data center scale. You will partner with silicon, hardware, firmware, infrastructure, manufacturing, operations, and security teams to define and deliver system-level device trust. This includes boot integrity, device identity, provisioning, attestation, management-plane security, storage encryption, debug controls, firmware update and recovery, RMA, and decommissioning. You will be accountable for turning threat models into requirements, requirements into implementation, and implementation into validation evidence that can support launch decisions. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Own security requirements, threat models, validation strategy, and launch-readiness evidence for first-party hardware platforms from early design through production deployment. Design and review secure boot, measured boot, roots of trust, platform firmware resilience, firmware signing, recovery, and anti-rollback strategies across heterogeneous devices. Own device identity, provisioning, enrollment, attestation, certificate lifecycle, and key-management requirements across manufacturing and data center bring-up. Harden management

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We're seeking a System Software Engineer to join our First-Party Hardware team. In this role, you will design, build, integrate, and validate low-level system software for the manageability and health of OpenAI's first-party AI hardware systems. You will work across BMC, Linux, firmware interfaces, automation infra, boot and recovery, hardware diagnostics, telemetry, host and platform drivers, network software interfaces, and manufacturing and fleet readiness. A major part of this role is owning the acceptance path for partner-delivered system software: defining requirements, reviewing code and artifacts, reproducing builds, building tests, pushing fixes, and producing the evidence needed for launch decisions. This role is hands-on and high-ownership. You will write and review low-level software, debug issues across hardware and software boundaries, build infra and automation to test and manage devices in lab, guide partner deliverables, build validation evidence, and help carry platforms from bring-up through production deployment. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role, you will: Design, develop, and maintain low-level firmware and system software for first-party AI hardware manageability, including BMC software, Redfish services, gNMI telemetry, firmware update and recovery flows, BIOS/UEFI interactions, platform drivers, and hardware diagnostics. Own integration and acceptance of partner and ve

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. The Compute team works on the design of our AI supercomputers, doing everything from workload modeling to influencing accelerator design. We’re leaning into our partnerships to make system and data center co-design an integral part of this process, and are looking for engineers to design AI supercomputers solutions for data center applications This team is responsible for working with partners to optimize their hardware for our workloads, identifying promising new deep learning accelerators, and bringing those hardware platforms to production. If you’re excited to work at the intersection of cutting edge deep learning, hardware system, and data center design this role is for you! About the Role We’re looking for a Product Reliability Engineer to own reliability engineering for advanced IT hardware, from printed circuit board assemblies (PCBAs) through compute and networking trays, systems, and fully integrated racks. You’ll translate operating conditions and service-life goals into reliability requirements, design and execute qualification tests, and drive failure analysis and corrective-action verification from development through production and field deployment. Working with electrical, mechanical, thermal, manufacturing, quality, and data center teams, suppliers, and manufacturing partners, you’ll use test and field evidence to improve hardware durability, serviceability, and availability. This role

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. In this role you will: As a Hardware Test Engineer, you will work on Machine Learning/AI hardware system projects to craft the solutions for current and future data center deployments. You will bring a strong understanding of hardware system testing, excellent project management skills, and the ability to collaborate across multiple teams to ensure efficient lab operations. You will be responsible for designing, implementing, and executing comprehensive test plans that ensure the reliability, performance, and scalability of our supercomputing hardware systems. You will develop detailed test plans and methodologies tailored to hardware components, including processors, memory modules, custom accelerators and interconnects. You will collaborate with hardware design, manufacturing, firmware teams and vendors to identify, analyze, and resolve issues affecting hardware, power, thermal and high-speed interconnects. You will perform in-depth debugging on the hardware system Excellent analytical skills to diagnose hardware issues, troubleshoot problems, and propose solutions. Ability to interpret complex test data, identify trends, and draw meaningful conclusions. High-speed links, with a focus on SerDes (Serializer/Deserializer) technology to assess signal integrity, error rates, and overall link performance. You will collaborate with the lab manager to maintain the equipment and hardware systems, including oscilloscopes, thermal test chambers, liquid cooling systems, and other mea

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery. In this role you will: Define the architecture and technical roadmap for custom SoCs targeted for edge applications. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments. Collaborate with internal hardware, software, systems, and product teams to align architecture with platform needs. Partner with external silicon vendors, IP providers, and manufacturing partners to execute development plans. Lead hardware/software co-design efforts to maximize performance per watt and end-to-end system efficiency. Guide implementation teams through microarchitecture, RTL development, validation, and bring-up phases. Operate effectively in agile development environments and help teams deliver against aggressive schedules and milestones. You might thrive in this role if: Proven exper