Methodology Jobs

ASIC Methodology, Flow and Integration Engineer — 2 Locations. Apply via Workday.

Design Methodology – Senior / Staff DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Design Methodology – Principal DRAM Power Integrity Engineer — Hyderabad - Phoenix Aquila, India. Apply via Workday.

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA Silicon Codesign Group is seeking a versatile engineer to join the HW bring-up methodology team. The SCG team is uniquely positioned to have an end-to-end view of the product development cycle - from early architecture definition, through bringup, to product release. What will you be doing: Led end-to-end planning and on-time execution of Nvidia's new chip bringup effort, from pre-silicon through production deployment. Coordinate multi-functional teams across Architecture, Build, Validation, DFT, SW, System, and Operations to drive shared bringup achievements. Improve cross-team communication, work, and handoffs. Develop and standardize methodologies, processes, and workflows for silicon bringup, creating reusable checklists and playbooks. Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules. Lead post-action reviews and convert learnings into concrete process improvements for future silicon and solution bringups. Contribute to post-silicon learnings that feed back into architecture, design, and pre-silicon

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (T

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-X Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions in AI for Chip Design and AI for Predictions in various use cases in manufacturing testing on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas. This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs. You will work with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips. You will work on post-silicon data analysis for power to architect the next-gen solutions. In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equ

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work with pre-silicon and post-silicon data analytics - visualization, insights and modeling. Design and uphold sturdy data pipelines and ETL processes for the ingestion and processing of DFX Engineering data from various origins Lead engineering efforts by collaborating with cross-functional teams (execution, analytics, data science, product) to define data requirements and ensure data quality and consistency You will work on hard-to-solve problems in the Design For Test space which will involve application of algorithm design, using statistical tools to analyze and interpret complex datasets and explorations using Applied AI methods. In addition, you will help develop and deploy DFT methodologies for our next generation products using Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 5+, MSEE with 3+, or PhD wi

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. What you’ll be doing: As part of Operations Engineering team that plays a key role in developing new IC products, you will design, develop, and implement cost-effective methods of ATE testing. Offer creative solutions to improve test methodology of existing solution. ATE test method code debugging and development Scripting tools debugging and development Web-based tools debugging and development Help to solve production issues or throughput issues that might be related to test methodology What we need to see: Master/Bachelor degree in Engineering or Science 5+ years related working experience In-depth knowledge and hands-on experience in Advantest 93K ATE or other ATE platform Good skills in programming languages such as C/C++ or Java Strong problem-solving capability English communication capability is required Strength in presenting to technical audiences and generating content for developers Critical thinking, solution focused and attention to detail Ways to stand out from t

Senior STA Signoff Methodology Engineer — 2 Locations. Apply via Workday.

CPU Design Methodology Engineer — 4 Locations. Apply via Workday.

CPU Design Methodology Engineer — 4 Locations. Apply via Workday.

Senior CPU Front End Methodology Engineer — 3 Locations. Apply via Workday.

Engineer, DDEG Design Methodology — Hyderabad - Phoenix Aquila, India. Apply via Workday.

SR ENGINEER, DDEG Design Methodology — Hyderabad - Phoenix Aquila, India. Apply via Workday.

MANAGER, DDEG DESIGN METHODOLOGY — Hyderabad - Phoenix Aquila, India. Apply via Workday.