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NVIDIA is leading the way in groundbreaking developments in Artificial Intelligence, High Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables amazing creativity and discovery, and powers what were once science fiction inventions from artificial intelligence to autonomous cars. We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. We are looking for a motivated Performance engineer to influence the roadmap of our communication libraries. The DL and HPC applications of today have a huge compute demand and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! This is an outstanding opportunity for someone with HPC and performance background to advance the state of the art in this space. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Conduct in-depth performance characterization and analysis on large multi-GPU and multi-node clusters. Study the interaction of our libraries with all HW (GPU, CPU, Networking) and SW components in the stack Evaluate proof-of-concepts, conduct trade-off analysis when multiple solutions are available Triage and root-cause performance issues reported by our customers Collect a lot of performance data; build tools and infrastructure to visualize and analyze the information <li

NVIDIA is leading groundbreaking developments in Artificial Intelligence, High Performance Computing and Visualization. The GPU -- our invention -- serves as the visual cortex of modern computers and is at the heart of our products and services. Our work opens up new universes to explore, enables groundbreaking creativity and discovery, and powers inventions that were once considered science fiction, including artificial intelligence to autonomous cars. We are the GPU Communications Libraries and Networking team at NVIDIA. We build communication libraries like NCCL, NVSHMEM, and UCX that are crucial for scaling Deep Learning and HPC. We're seeking a Senior Software Architect to help co-design next-gen data center platforms and scalable communications software. DL and HPC applications have a huge compute demands and already run at scales of up to tens of thousands of GPUs. GPUs are connected with high-speed interconnects (e.g. NVLink, PCIe) within a node and with high-speed networking (e.g. InfiniBand, Ethernet) across nodes. Efficient and fast communication between GPUs directly impacts end-to-end application performance. This impact continues to grow with the increasing scale of next generation systems. This is an outstanding opportunity to advance the state-of-the-art, break performance barriers, and deliver platforms the world has never seen before. Are you ready to build the new and innovative technologies that will help realize NVIDIA's vision? What you will be doing: Investigate opportunities to improve communication performance by identifying bottlenecks in today's systems. Design and implement new communication technologies to accelerate AI and HPC workloads. Explore innovative solutions in HW and SW for our next generation platforms as part of co-design efforts involving GPU, Networking, and SW architects. Build proofs-of-concept, conduct experiments,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Support the New Production Introduction (NPI) / Tech Node (TN) Process - Coordinate and facilitate Phase Gate meetings - Work with Package Development Engineering (PDE) / Advance Product Technology Development (APTD) and define required Phase Gate / PMI milestones to meet HVM required date. - Work with Package Development Engineering (PDE) / Advance Product Technology Development (APTD) for PG/PMI report preparation, process flow & readiness check and E2E monitoring. - Work with Package Development Engineering (PDE) / Advance Product Technology Development (APTD) for LVM facilitator & healthy monitoring. - Partner with technology development teams on milestones and product validation. - Applying AI for NPI critical lot tracking and NPI tool fanout activities. - The other NPM PLM Track all Managed new product development against milestones - Plan and drive schedules to ensure on-time execution - Ensure the schedule and resource data is current, accurate and up to date - Ensure milestones are created for new product requests - Follow up on issues that delay project milestones - Ensure smooth execution of product requests and adherence to NPI methodology - Ensure methodology and process documentation adhere to the best quality standards About Micron Technology, Inc. We are an industry leader in innovative memory

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . ​ Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities: The layout manager needs to lead Layout planners to provide layout strategy and solutions for Fab scale expansion and tech node migration with the best Fab space and operational efficiency and cost effectiveness. Enhance site scenario process with intelligent layout, transfer, and tool utility systems with the flexibility to changes. Develop long term strategy plan and intelligent system for space planning. Key Job: Layout team management and people development. Coordinate and collaborate with teams to optimize space and operational efficiency across Fab, lab, and supporting functions through BKM practices, competitive space cost, and flexibility for future expansion. Collaborate with TIQ (Tool Installation and Qualification) team to plan tool move-in/out activities and release tool on time to meet business needs. Develop long-term space strategies and build/remodel innovative, intelligent Fabs. Continuously define and improve standardized processes and methodologies for layout planning and optimization. Develop and implement AI-enabled

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a PI Magin Bin and ESPEC manager, you will lead a team of highly skilled PI Margin Bin and ESPEC engineers with the goal of introducing new tech-node and optimizing DRAM process flow while ensuring stable fab output and maintaining product quality in OMT. You will interact with a wide variety of engineering and production teams within and outside OMT to achieve the company’s goals. Also, adopt AI agent tools to strengthen job function competitiveness continuously. Responsibilities and Tasks Lead and manage a team of engineers to successfully implement innovative solutions Coordinate the development and execution of technical projects and initiatives Ensure flawless execution of projects by strictly adhering to quality and performance standards Collaborate with cross-functional teams to determine project requirements and deliverables Provide mentorship and guidance to team members to foster growth and development Monitor and analyze project performance to identify areas for improvement and implement corrective actions Stay up-to-date with industry trends and advancements to maintain our competitive edge Develop and maintain relationships with key collaborators to support project goals Required skills and experience to succeed in this role, you will need as following, Proven experience in a managerial engineering role Strong leadership skills with the ability to encourage and motivate a team Outstanding

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a PI Margin Bin and ESPEC manager, you will lead a team of highly skilled PI Margin Bin and ESPEC engineers with the goal of introducing new tech-node and optimizing DRAM process flow while ensuring stable fab output and maintaining product quality in OMT. You will interact with a wide variety of engineering and production teams within and outside OMT to achieve the company’s goals. Alos, adopt AI agent tools to strengthen job function competitiveness continuously. Responsibilities and Tasks Lead and manage a team of engineers to successfully implement innovative solutions Coordinate the development and execution of technical projects and initiatives Ensure flawless execution of projects by strictly adhering to quality and performance standards Collaborate with cross-functional teams to determine project requirements and deliverables Provide mentorship and guidance to team members to foster growth and development Monitor and analyze project performance to identify areas for improvement and implement corrective actions Stay up-to-date with industry trends and advancements to maintain our competitive edge Develop and maintain relationships with key collaborators to support project goals Required skills and experience to succeed in this role, you will need as following, Proven experience in a managerial engineering role Strong leadership skills with the ability to encourage and motivate a team Outstanding

About the Job Set the performance direction behind large-scale AI systems built for real deployment. As a Principal AI Performance Engineer, you will define how Graphcore analyzes and optimizes AI training and inference workloads. Your work will shape decisions across hardware, software, networking and system architecture. You will lead the hardest performance investigations, from model behavior to multi-node scaling. You will turn profiling, benchmarking and modeling evidence into technical roadmaps and engineering priorities. You will set measurement standards, guide distributed communication strategy and review critical C++ and Python tools. Your judgment will help teams make better decisions when data is incomplete. This role gives you rare influence across AI infrastructure at data center scale. It is based in Austin, Texas. The team and culture The System Engineering Performance team architects, evaluates and optimizes high-performance infrastructure for large-scale data center deployments. The team works across the computing stack to understand real system behavior. Work happens through evidence, technical ownership and direct cross-team influence. You will guide strategy, resolve complex tradeoffs and raise performance-engineering standards across the organization. Decisions are shaped by benchmarks, simulations, models and clear technical debate. The team values engineers who think big, act fast, take responsibility, speak up and lead beyond their own area. What we’re looking for · Deep experience profiling and optimizing AI, machine learning or high-performance computing workloads at scale. · Proven technical leadership across complex performance-engineering or system-architecture initiatives. · Expert C++ and Python skills, including reliable tools or performance-sensitive software. · Expert understanding of compute, memory, communication and scaling behavior in distributed systems. · Ability to define benchmarks, measurement practices or optimization sta

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron’s NAND Process Development (PD) Singapore group is looking for Senior Process Development Engineer to join Advanced Node team to support TD activities associated with rapid deployment of technology nodes, the process margin improvement work necessitated thereof as well as to ensure extended engagement with manufacturing on the upcoming technology nodes. Main Responsibilities: As a CMP Process Development Engineer, you will be primarily responsible for developing and optimizing CMP processes to improve product quality and reliability for the next generation of Micron's memory parts. Focus on understanding and improving the process margins required for meeting the mature yield goal for 3D NAND parts. Advanced 3D NAND CMP process development will include performing fundamental research, consumables development, and hardware evaluation, as well as testing processes for novel applications. Initiate and manage experiments to widen process margins as well as to evaluate manufacturability of next node solutions. Ext

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Micron’s NAND Process Development (PD) Singapore group is looking for Senior Process Development Engineer to join Advanced Node team to support TD activities associated with rapid deployment of technology nodes, the process margin improvement work necessitated thereof as well as to ensure extended engagement with manufacturing on the upcoming technology nodes. Main Responsibilities: As a CMP Process Development Engineer, you will be primarily responsible for developing and optimizing CMP processes to improve product quality and reliability for the next generation of Micron's memory parts. Focus on understanding and improving the process margins required for meeting the mature yield goal for 3D NAND parts. Advanced 3D NAND CMP process development will include performing fundamental research, consumables development, and hardware evaluation, as well as testing processes for novel applications. Initiate and manage experiments to widen process margins as well as to evaluate manufacturability of next node solutions. Ext

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Technology Development Operations team enables successful process node development by optimizing manufacturing execution, accelerating learning cycles, and supporting breakthrough delivery within Micron's semiconductor fabrication environment. The team uses data analytics, automation, operational planning, and AI-enabled tools to improve manufacturing performance, drive operational efficiency, and support next-generation technology development. As a Technology Development Operations Engineer, you will drive data-informed manufacturing execution and operational performance across technology development programs. You will partner with engineering, manufacturing, industrial engineering, and operations teams to optimize work-in-progress (WIP) flow, improve cycle times, support starts planning, manage operational risks, and develop analytics and automation solutions that accelerate technology development achievements. Responsibilities Monitor and improve manufacturing performance metrics including WIP, cycle time, throughput, inventory positioning, part turns, and operational constraints to support technology development achievements. Analyze manufacturing data, identify root causes of process and operational issues, and develop recommendations that improve line performance, learning cycles, and execution efficiency. Develop analytics, dashboards, forecasting models, and automation solutions to improve visibility, planning accuracy, operational decision-making, and reporting. Support starts

We are the GPU Communications Libraries and Networking team at NVIDIA. We deliver communication libraries like NCCL, NVSHMEM, UCX for Deep Learning and HPC. DL and HPC applications have a huge compute demand already and run on scales which go up to tens of thousands of GPUs. The GPUs are connected with high-speed interconnects (eg. NVLink, PCIe) within a node and with high-speed networking (eg. Infiniband, Ethernet) across the nodes. Communication performance between the GPUs has a direct impact on the end-to-end application performance; and the stakes are even higher at huge scales! We are looking for a technical leader to manage our NVSHMEM and UCX libraries. This is an outstanding opportunity to push the limits on the state-of-the-art and deliver platforms the world has never seen before. Are you ready for to contribute to the development of innovative technologies and help realize NVIDIA's vision? What you will be doing: Lead, mentor, and grow your library engineering team and be responsible for the planning and execution of projects as well as the quality, and performance of your libraries. This is a technical leadership role so you will participate in feature design and implementation. Interact with internal and external partners and researchers to understand their use cases and requirements. Collaborate with engineering teams, program and product management, and partners to define the product roadmap. Continuously review and identify improvement opportunities in established processes, infrastructure, and practices to ensure the teams are executing in the most efficient and transparent manner. What we need to see: 10&#43; overall years of experience in the software industry with specialization in HPC networking or system software. 4&#43; years of management experience. BS, MS, or Ph.D. in C

Job Details: Job Description: Shape the Future of Semiconductor Innovation at Intel Foundry Organization Overview Manufacturing Development Customer Engineering (MDCE) is a newly established organization within Intel Foundry Technology Manufacturing and is focused on accelerating technology ramp and manufacturing excellence. Our mission is to seamlessly transition cutting-edge technologies from development to high-volume production while making technology ramp a key competitive differentiator for Intel Foundry. Position Summary MDCE is seeking a Staff Chemical Mechanical Planarization (CMP) Engineer to drive module ownership and technical leadership across Intel's most advanced logic technologies (18A, Intel 3, Intel 12nm). This role requires a seasoned professional who can navigate the complexities of process development, cross-node standardization, and high-volume manufacturing readiness while delivering exceptional results for both Intel products and foundry customers. Core Responsibilities Technical Leadership Process Development & Optimization: Lead CMP process development from concept through HVM implementation across multiple advanced technology nodes Cross-Node Alignment: Drive standardization and best practices across Intel's technology portfolio to maximize efficiency and yield Problem Resolution: Own and resolve complex CMP-related yield and manufacturing issues using data-driven approaches and structured problem-solving methodologies Strategic Execution Customer-Centric Delivery: Align technical strategies with customer requirements and business objectives, ensuring on-time delivery of robust solutions Technology Transfer: Bridge technology development and manufacturing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Coordinate the P&L for the vEIM DRAM product line serving embedded markets. Define and carry out approaches to increase revenue and market share in Automotive, Industrial, and Consumer verticals while maintaining product line profitability. Develop positive relationships with engineering, technology development, and quality organizations to deliver outstanding products with differentiated features that surpass customer requirements. Establish effective financial and business analyses and processes to justify and approve next-generation products. Drive speedy resolution of customer issues seen during qualification and production. Define marketing strategies to drive demand creation while effectively handling supply, demand, and inventory. Define long-term DID and node longevity strategy for the product line. Define pricing strategies to meet product line objectives. Define and complete go-to-market plans for new products, including collateral, field training, and outbound messaging. Education & Ideal Experience Degree or equivalent experience in Electrical Engineering, Computer Science, or a related field and/or advanced education in business administration. 10&#43; years of progressive marketing leadership and industry experience. Extensive semiconductor experience with a deep understanding of DRAM and memory markets. Extensive background in developing and introducing products, combined with understanding of

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Position Overview: As a Staff/Principal Equipment Engineer within PROCT ADT, you will provide technical leadership to improve equipment performance, capability, and global manufacturing outcomes. You will lead complex, multi-site initiatives to resolve equipment challenges, enable technology node readiness, and drive yield and defectivity improvements. This role requires deep expertise, strong ownership, and the ability to influence across teams and suppliers to deliver measurable impact in cost, performance, and scalability. Responsibilities Lead global ownership of equipment performance across toolsets, driving improvements in stability, availability, matching, and efficiency. Direct complex, multi-fab root cause analysis for equipment-driven yield, defectivity, and reliability issues using data-driven and physics-based approaches. Provide technical leadership in tool hardware and chamber behavior to expand process capability and improve performance limits. Partner with Technology Development, integration, and process teams to enable node readiness, volume ramp, and disciplined change control. Influence equipment supplier strategy by leading technical engagements, driving design improvements, and aligning roadmaps to business needs. Drive global standardization through development, validation, and deployment of Best Known Methods (BKMs) across sites. Lead initiatives to improve cost of ownership, reduce variation,

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE Drive the technical foundation and supply integrity of Everpure’s enterprise flash arrays, blades, and server building blocks as Component Engineering Manager. You will lead a high-performing engineering team and serve as the final authority on component qualification, ensuring every storage node, CPU, memory subsystem, and interconnect module meets uncompromising performance and reliability standards. By bridging Hardware Engineering, Quality, Supply Chain, and global semiconductor vendors, you will directly influence product architecture while safeguarding manufacturing continuity and operational scale. WHAT YOU'LL DO Engineering Leadership & Talent Development: Build, direct, and mentor a specialized team of component engineers spanning flash/SSD technologies and server platform hardware, fostering technical growth and setting execution priorities. End-to-End Component Qualification: Own the complete qualification lifecycle—defining rigorous test plans, analyzing supplier data, and issuing final approval for design-in and mass production across NAND flash, CPUs, DRAM, power systems, and interconnects. Strategic Flash & SSD Oversight: Drive roadmap alignment and technology node transitions with key storage suppliers, governing media characterization, firmware qualification, and long-term architectural integration. Supply Resilience & Risk Mitigation: Establish multi-sourcing strategies, lead s