Packaging Area Shift Engineer Jobs

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats. Collaborate with OSATs and material suppliers to qualify mold and underfill materials, define dispense and cure equipment requirements, and manage process transfers into production. Lead characterization of mold and underfill material properties (viscosity, gel time, cure kinetics, adhesion, CTE, modulus) and correlate material behavior to process outcomes and package reliability. Work closely with thermal mechanical modeling teams to model solder joint reliability of bump interconnects with va

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

What We're Looking For: We're looking for photonics packaging engineers to contribute to, and own aspects of the A-0 and A-1 packages. This role bridges the classically divided photonics and advanced packaging skillsets, and thus is an unique point in our team. Ideal Background: Experience with integrated photonics package assemblies with multiple dies Experience with integrated circuit MCM assemblies with multiple heterogeneous materials, including compound semiconductors Understanding of photonics concepts, such as mode field diameters, mode mismatch, polarization, etc. Nice to Have: Experience with large device count photonic assemblies Experience with clear underfill Experience with high density fiber attach Experience with large substrate size photonic MCM assemblies Hands-on experience with PIC design

About the Role You will contribute to and own aspects of the Volantis A-0 and A-1 package. We are interested in both people with package design as well as package process development backgrounds Our end goal has challenges to overcome in warpage, CTE mismatch, thermomechanical aspects, assembly speed and more. We're building a wafer-scale package with both silicon and compound semiconductor dies sitting together at very high TDP. This creates both unique challenges and opportunities. The end result is breaking the memory wall, enabling a new era of AI, and a platform that scales another 1-3 orders of magnitude. What We Look For Ability to think from first principles about novel problems- not just applying existing solutions outside of their range of application. What works for 5x reticle platforms may not work for 56x reticle platforms Design or process development of complex packages Nice to Have: Experience with heterogeneous material assemblies Experience with high-TDP packages Experience with compound semiconductor assemblies Experience with co-packaged optics Ability to work with architects to co-design system architecture and package design Experience with interposer platforms such as CoWoS, CoWoS-L, CoWoS-R, EMIB, FoCoS, FoCoS-Bridge, etc Experience with flip-chip integration, especially mass reflow, TCB & LAB Experience with large scale (>50x50mm) substrates Compensation Package: Competitive Base salary + Significant Equity Stake. You'll be well compensated while also owning a piece of the outcome. California Pay Range: $250K-$400K

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. A Brief Overview Collaborates with the dispensing pharmacists and pharmacy technicians to accurately and efficiently prepare patient medication orders, package customer orders for shipment, and receive and stock supplies. What you will do Gathers orders for shipment in accordance with company specialty guidelines. Prepares labels and ships orders based on pharmacy guidelines and best practices. Maintains the stock in the warehouse area to record monthly inventory reviews. Collects information pertaining to restocking of packing stations with shipping supplies to ensure sufficient resources are allocated. Composes sorting order forms based on courier and class of service to ensure information is clear. Monitors unlocking stations, trains new operations assistants, and scans data multi-piece handling. Follows workflow, orders packing supplies and performs monthly audits when applicable. Gathers pharmacy files and records in accordance with internal procedures to ensure organizational standards of the company are met. For this role you will need Minimum Requirements Basic awareness of problem solving and decision making skills Valid state pharmacy technician or technician trainee license . Minimum of 6 months general work exper

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. A Brief Overview Collaborates with the dispensing pharmacists and pharmacy technicians to accurately and efficiently prepare patient medication orders, package customer orders for shipment, and receive and stock supplies. What you will do Gathers orders for shipment in accordance with company specialty guidelines. Prepares labels and ships orders based on pharmacy guidelines and best practices. Maintains the stock in the warehouse area to record monthly inventory reviews. Collects information pertaining to restocking of packing stations with shipping supplies to ensure sufficient resources are allocated. Composes sorting order forms based on courier and class of service to ensure information is clear. Monitors unlocking stations, trains new operations assistants, and scans data multi-piece handling. Follows workflow, orders packing supplies and performs monthly audits when applicable. Gathers pharmacy files and records in accordance with internal procedures to ensure organizational standards of the company are met. Compensation: Starting pay rates are based on experience, ranging from: $19.25-20.83/hr Required Qualifications Minimum of six months general work experience Must be a

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. A Brief Overview Collaborates with the dispensing pharmacists and pharmacy technicians to accurately and efficiently prepare patient medication orders, package customer orders for shipment, and receive and stock supplies. Position Summary This position works with the dispensing pharmacists and pharmacy technicians to accurately and efficiently prepare patient medication orders, package customer orders for shipment, receive and stock supplies and various other duties. What you will do Gathers orders for shipment in accordance with company specialty guidelines. Prepares labels and ships orders based on pharmacy guidelines and best practices. Maintains the stock in the warehouse area to record monthly inventory reviews. Collects information pertaining to restocking of packing stations with shipping supplies to ensure sufficient resources are allocated. Composes sorting order forms based on courier and class of service to ensure information is clear. Monitors unlocking stations, trains new operations assistants, and scans data multi-piece handling. Follows workflow, orders packing supplies and performs monthly audits when applicable. Gathers pharmacy files and records in accordance with internal procedures to ensure organizational standards of the company are met. Required Qualificatio

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary: Micron is seeking motivated Process Technician within the Advanced Packaging Technology Development (APTD) department. This role is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Micron is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. By collaborating closely with our global R&D, equipment and materials suppliers, and manufacturing teams, we ensure the efficient development, transfer and implementation of new technology nodes, maintaining Micron's leadership in the industry. As a Manufacturing Process Technician, you will be responsible for monitoring, maintaining, and improving equipment performance in collaboration with operations teams, engineers, and vendors. Your role includes performing preventative maintenance, troubleshooting mechanical and software issues, and ensuring efficient product flow. You will also support cycle time reduction by addressing tool inefficiencies, verifying lot processing, and analyzing workstation performance to drive continuous improvement. Job Responsibilities: Complete required safety training and consistently follow safety protocols during all work activities. Identify and resolve chronic inefficiencies through continuous improvement initiatives, training, or area suggestions. Review and p

Role Overview We are seeking a Senior Micro-Optics/Microlens Array Engineer to design, model, and validate microlens-array and wafer-level micro-optical components for high-density photonic packages. You will translate system-level optical requirements into manufacturable designs, build tolerance budgets, work with fabrication and packaging partners, and close the loop with measured data. Candidate note: We do not expect one person to match every item below. Strong candidates from micro-optics, optical packaging, semiconductor photonics, lithography/process integration, precision optics, or FDTD-Zemax co-design backgrounds are encouraged. What You Will Do Own micro-optical design: design microlens arrays and compact micro-optical components, including lens pitch, aperture, focal length, numerical aperture, sag, surface form, fill factor, array uniformity, substrate, material, and coating choices. Build connected optical models: use tools such as Zemax OpticStudio, Code V, FRED, LightTools, VirtualLab, Ansys/Lumerical, COMSOL, or equivalent; combine ray, physical-optics, diffraction, and statistical methods where appropriate. Bridge EM-scale and package-scale design: where useful, connect FDTD, FEM, EME, RCWA, or similar electromagnetic simulations to Zemax/Code V/physical-optics models so local optical-interface behavior is represented in system-level trade studies. Drive tolerancing and yield: develop sensitivity studies and tolerance budgets across fabrication, placement, package stack-up, adhesive, thermal, refractive-index, coating, and surface-form variation; use Monte Carlo and DOE methods to connect design choices to expected yield. Bring semiconductor process awareness: partner with process and supplier teams across lithography, grayscale/direct-write patterning, imprint, etch transfer, deposition, thin-film coatings, wafer-level metrology, design rules, and process-window trade-offs. Translate design intent: create vendor-ready specifications, optica

About the Team Netlify runs on usage. Developers buy credits, teams consume compute and bandwidth, and enterprises commit to spend. The Accounts and Billing area owns how all of that works: the accounts foundation every customer signs into, the billing platform that meters and charges them, and the pricing and packaging model that sets what they pay. It sits at the center of how Netlify grows, and it touches Finance, Growth, UX, Sales, and the executive team. As a Staff Product Manager, you’ll help define and evolve Netlify’s monetization model, bringing a strong point of view while partnering across the company to make high-impact decisions, and you will build hands-on next to engineering, Finance, and design rather than run a team from above. You’ll collaborate closely with senior leaders, including the CEO and CFO, as we continue to evolve Netlify’s pricing and packaging strategy. What You'll Do Lead the strategy and evolution of pricing, packaging, and monetization, including plans and tiers, the credit and usage model, seat-versus-consumption economics, on-demand and overage rates, enterprise commitments and discounting, storage pricing, regional pricing, and annual plans. Ship billing as a product: metering accuracy, invoicing, payments, refunds, and customer-facing usage visibility, including the billing and usage interfaces enterprises are asking for. Steward the accounts foundation: sign-up and authentication, identity, orgs and teams and seats, roles and permissions, account security, and fraud and abuse at the top of the funnel. Build and lead the pricing and packaging experimentation program, using data, customer insight, and sound judgment to guide decisions: product analytics, conversion and activation, and credit-consumption telemetry. Partner with Finance to develop pricing approaches that balance customer value, business goals, and long-term sustainability. Partner with engineering and cross-functional stakeholders to set priorities, evaluate tradeo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an SoC Physical Design Senior Manager, HBM in the Heterogeneous Integration Group (HIG), you will lead a team of physical design and physical verification engineers responsible for implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tapeout. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Recruit, develop, and mentor a team of physical design engineers delivering HBM base die products. Plan project resourcing requirements and timelines. Prioritize resources across projects and individual assignments to meet aggressive product delivery schedules. Drive physical implementation for SoC blocks and/or top-level including floorplanning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Collaborate with design and integration teams to ensure clean implementation of clocking/reset strategy, power architecture, and SoC integration requirements. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust

The Senior Product Manager is a core Individual Contributor (IC) product role responsible for leading a complex, business-critical product area with significant dependencies, owning high-impact roadmap and product decisions over a multi-year horizon for the Client Libraries portfolio (MongoDB drivers across many programming languages, Object Document Mappers, and App Framework integrations) at MongoDB. You move beyond what data confirms to anticipate where customer needs and competitive dynamics are heading before the data makes it obvious, acting effectively even when signals are incomplete. You serve as a go-to domain expert and mentor across Product, Engineering, Design, and Go-To-Market (GTM) teams, turning ambiguous opportunities into clear business cases and leading cross-functional execution for developer-facing SDKs, drivers, ODMs (e.g., Mongoose, Entity Framework Core, Hibernate, Django), and framework ecosystems (Drizzle, Feast). This role can be in-office, flexible (hybrid), or remote in the United States. Responsibilities Vision & Strategy: Convert company and organizational strategy into a compelling vision and multi-year roadmap for the Client Libraries portfolio, making independent prioritization calls under incomplete information regarding major languages driving MongoDB Atlas growth, fast-growing ODMs, and strategic language communities Anticipatory Customer Discovery: Maintain deep market and customer knowledge across a complex domain, reading subtle signals across developers, framework maintainers, and enterprise buyers to anticipate unstated customer needs and competitive dynamics (including how AI-native tooling is reshaping developer expectations) Business Cases & Monetization: Turn ambiguous or untapped opportunities within or adjacent to your domain (such as new language drivers, framework integrations, or driver capabilities) into clear, actionable business cases, including packaging, adoption strategy, and revenue implications for M

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r