Physical Therapist Assistant Jobs

What You'll Do Physical scientist/engineer to take responsibility for testing and validation of novel hardware systems What We're Looking For Hands-on laboratory experience and the ability to work independently Familiarity with test and measurement equipment including: oscilloscopes, lock-in amplifiers, spectrum analyzers, PID controllers, etc. Proven diagnostic and troubleshooting skills, coupled with the drive to understand experimental results fully before proceeding Diligent record-keeping habits and facility with Python/Matlab/equivalent for data analysis and visualization Ability to work on-site (up to five days/week) in the San Francisco Bay Area Given the nature of the work, U.S. citizenship is required. Useful Experience Background in experimental physics, particularly in quantum or optical measurements Hands-on EE design and manufacturing experience: analog and digital electronics, board layout, soldering, etc. Excellent data presentation skills A desire to learn new skills outside your current area of expertise Proficiency using the latest AI tools to accelerate workflow

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team and is central to delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators. You’ll work closely with RTL designers to define and execute on physical design strategies. You will develop tools, flows and methodologies to increase team productivity. Your work will directly impact silicon’s performance and cost efficiency, as well as the team’s execution velocity and quality. In this role, you will: Develop, build and own tools, flows and methodologies for physical implementation Own physical implementation of floorplan blocks from floorplanning to final signoff Collaborate with RTL designers to drive optimal block implementation solutions Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners Qualifications: BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development Demonstrated success in taping out complex silicon designs Hands-on experience with block physical implementation and PPA convergence Strong coding experience with python, bazel, TCL Strong experience building physical design tools, flows and methodologies Strong understanding of microarchitecture, RTL design,

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives the implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes. This role combines deep physical design expertise with organization-level technical leadership, enabling predictable RTL-to-GDS execution, strong PPA outcomes, and scalable methodology adoption across multiple projects and teams. This role is remote based out of the United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are You are an experienced Physical Design Engineer with 10+ years of ASIC/SoC/CPU experience, ideally focused on high-performance CPUs or similarly complex digital designs. You bring deep expertise across RTL-to-GDS implementation and signoff, including timing closure, power optimization, SI, EM/IR, extraction, and physical verification. You have built or owned physical design methodology, automation, or CAD flows and are highly skilled in Tcl, Python, Perl, or similar scripting languages. You are a technical leader who can influence across teams, mentor engineers,

About the Team OpenAI’s Forward Deployed Engineering team partners with leading semiconductor companies to deploy production-grade AI systems across the entire chip design lifecycle: design, verification, and physical design. We operate at the intersection of customer delivery and core platform development, embedding deeply with customers to translate frontier model capabilities into systems that materially improve engineering workflows and accelerate innovation. Our work turns early, high-touch deployments into repeatable solution patterns, reference architectures, and evaluation practices that scale across the semiconductor ecosystem. About the Role We are seeking a highly skilled Physical Design Engineer to join our semiconductor-focused Forward Deployed Engineering team. This is a senior IC role that will begin with a strong emphasis on physical design expertise, technical judgment, advisory leverage, and customer credibility, with the expectation that the person will grow into a broader Forward Deployed Engineering role over time. In the near term, you will serve as the team’s physical design SME across semiconductor deployments: helping FDEs, Product, and Research understand backend implementation workflows, pressure-test AI-assisted solution ideas against real physical design constraints, and raise the quality of our customer-facing technical work. You will help the broader team build fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions in practice. Over time, we expect this role to expand beyond SME support into broader FDE ownership: partnering directly with customers, shaping deployment strategy, building and iterating production-grade AI systems, driving technical workstreams, and helping turn high-touch semiconductor deployments into repeatable solutions. This is a strong fit for someone who brings deep physical design expertise today and is excited to grow into a customer-facing, syst

Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, focusing on achieving robust, high-performance and power-efficient designs

Physical Design Power Optimization and Modeling Engineer — 2 Locations. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent licenses RISC-V and AI IP to customers who need hardened, PPA-proven deliverables on their target node and foundry. This role owns physical implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII signoff, and directly determines how fast we can commit to a customer's timeline. This role is hybrid, based out of Toronto, ON; Austin, TX; or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on physical design engineer who owns blocks end to end, with a track record of block-level and IP tapeouts on advanced nodes. Driven by PPA outcomes, working closely with RTL owners to close critical paths and hit power budgets. Rigorous about signoff quality, because our IP ships to customers who integrate it without you in the room. What We Need BS/MS/PhD in EE/ECE/CE/CS with 5+ years of block-level or IP-centric physical design through tapeout. Expertise with industry-standard tools (Innovus, ICC2/FusionCompiler, PrimeTime) and scripting languages (Tcl, Python, Perl). Deep understanding of advanced node challenges, low-power design (UPF, power gating, multi-Vt, voltage sc

What We’re Looking For: We’re looking for physical design engineers to help manage and execute the physical design process for the various dies that comprise our A-0 and A-1 systems. This will involve deciding what to do in-house and outsource, and then managing the outsourced process and integrating it with the in-house flow and effort. Ideal Candidates: Ideal candidates will have: Hands-on experience with the physical design process for at least one block in multiple advanced node tapeouts Ability to understand what PPA limiters are from RTL and coordinate with microarchitects to change the RTL to improve/fix them Experience both with in-house and outsourced physical design flows Nice to Have: Experience with physical design process for multi-die/multi-chiplet/MCM designs Experience with physical design process for reticle-max or near reticle max designs Experience with very high power density chips Experience with the physical design process for AI chips Experience with the physical design process of analog and mixed signal blocks and macros

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Our IP delivery timelines are set as much by flow maturity as by design work. This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start. This role is hybrid, based out of Toronto, ON; Austin, TX, or Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design or CAD methodology engineer who has built flows that production teams depend on daily. Automation-minded, happiest when you are removing manual steps and making PPA exploration repeatable. Building with AI as part of how you develop flows, and opinionated about where LLMs and ML-driven optimization genuinely help versus where they do not. An effective partner to design teams and EDA vendors, and a clear writer who documents flows well enough that others can run them without you. What We Need An Engineer with 5+ years developing and supporting physical design methodology or CAD flows in production use. Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (T

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Physical Security Assessments Team Lead – Semiconductor Manufacturing Job Summary We are seeking an experienced and talented Physical Security Evaluator to join our Physical Security Assessments team supporting semiconductor manufacturing operations in APAC. This position is responsible for leading and conducting comprehensive physical security evaluations of semiconductor critical manufacturing locations. You will join a team of experienced security professionals responsible for evaluating the effectiveness of physical security programs, including people, processes, technology, and protective measures. You will identify and document security vulnerabilities, assess risks to critical manufacturing operations and intellectual property, and provide recommendations to strengthen the security posture of our facilities. This role is responsible for developing detailed assessment reports and partnering with site leadership to im

Director of Engineering, Physical AI Role Overview The Director of Engineering will report to the General Manager of Physical AI, and will be responsible for leading a multi-disciplinary engineering organization. In this senior leadership role, you will own the execution of the Physical AI Data Engine — the platform powering the next generation of Physical AI/Embodied AI. You will collaborate closely with Operations and GTM to guide product direction and help solve the data bottleneck that stands between today's robotics research and real-world deployment. This role requires significant ownership in a fast-paced environment and you will motivate internal teams to set the pace for business growth. Travel will come into play. Key Responsibilities: Set and drive the technical vision across data collection infrastructure, teleoperation systems, ML training pipelines, model evaluation frameworks, annotation tooling, and research Lead a multidisciplinary engineering organization—spanning engineering managers, software engineers, ML engineers, and ML research scientists—while designing the organizational structure, talent strategy, and culture required to scale rapidly without compromising on quality or strategic alignment Maintain exceptional technical and operational excellence by deeply understanding team deliverables, asking incisive questions, identifying slipping standards early, and knowing precisely when to step in Drive cross-functional alignment across Engineering, Operations, and GTM on platform architecture, release processes, and shared priorities Collaborate with researchers and clients to architect and deliver scalable, production-grade data infrastructure tailored for complex robotics workloads Required Qualifications: Bachelor's degree in Engineering, Robotics, Computer Science, or a related technical field 8+ years of engineering experience in fast-paced environments, including 4+ years direct people management demonstrated history of recruiting, mentorin

Scale has been the leading AI data foundry, helping fuel the most exciting advancements in AI, including frontier model training, enterprise adoption, defense applications, and autonomous vehicles. Our mission is to develop reliable AI systems for the world's most important decisions. The next frontier for AI is the physical world. We're looking for an AI Product Manager to own the Robotics vertical within our Physical AI team. In this role, you'll own both the development of the data and training environments (the teleoperated demonstrations, real-world collections, simulated tasks, and annotation products that labs use to train and evaluate robot policies) and the "data as a product" strategy that powers them. You'll understand where physical AI is headed, decide what robot tasks and embodiments are worth collecting, how to source and structure the underlying data, and how to turn deep domain knowledge into a defensible product. The ideal candidate has lived inside robotics or physical AI research, and is able to pair that domain understanding with a sense for where current robot policies succeed and fail in real-world workflows. You'll translate that expertise into datasets, environments, and evaluation frameworks that teach robots to do real physical work, and you'll be the domain expert Scale's most important customers and their leading researchers turn to. A strong entrepreneurial & go-to-market mindset will be necessary. What You'll Do Own the Robotics AI roadmap & data strategy: Set product direction for the robotics training stack and the data strategy behind it — what data we collect, on which hardware and embodiments, and what we source internally vs. through our marketplace. Establish a vision for where physical AI is heading, driving execution across engineering, operations, and go-to-market teams. Build partnerships with research teams at frontier labs: Work directly with researchers at leading physical AI labs to understand where their robot p

Silicon Physical Design Engineer Multiple roles across different levels Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. The physical design team sits within the wider silicon design team which includes RTL, verification and DFT. Our work also involves strong links with architecture, packaging and product engineering. We are responsible for working with those teams to create high-quality RTL and building the final chip layout (e.g. GDSII) ensuring a signoff-quality design is delivered to the Foundry (e.g. TSMC). We are looking to hire high-quality silicon physical design engineers to join our team. The successful candidate will support the team with achieving our goals and creating the right engineering solutions. We are a collaborative team and good communication is essential, as is the ability to adapt and learn. For the successful candidate we offer an open, honest and collaborative environment working on leading-edge designs at the most advanced nodes. Our engineers are not siloed, and they are trusted and encouraged to ta ke ownership of their designs and problem solutions. You will be part of a team that looks for improvements to everything we do: our designs, our flows, our methodologies, our infrastructure. Responsibilities and Duties Applicants will be expected to contribute technically to the development of Graphcore's next generation of AI superchips, fo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Physical Security Assessments Team Lead – Semiconductor Manufacturing Location: Taiwan Travel: Up to 50% throughout Taiwan and Asia-Pacific manufacturing sites Job Summary We are seeking an experienced and talented Physical Security Evaluator to join our Physical Security Assessments team supporting semiconductor manufacturing operations in APAC. This position is responsible for leading and conducting comprehensive physical security evaluations of semiconductor critical manufacturing locations. You will join a team of experienced security professionals responsible for evaluating the effectiveness of physical security programs, including people, processes, technology, and protective measures. You will identify and document security vulnerabilities, assess risks to critical manufacturing operations and intellectual property, and provide recommendations to strengthen the security posture of our facilities. This role is responsible for developing detailed assessment reports and partnering with site leadership to implement corrective actions. As a Physical Security Assessment lead Evaluator, you wi

Employee Applicant Privacy Notice Who we are: Shape a brighter financial future with us. Together with our members, we’re changing the way people think about and interact with personal finance. We’re a next-generation financial services company and national bank using innovative, mobile-first technology to help our millions of members reach their goals. The industry is going through an unprecedented transformation, and we’re at the forefront. We’re proud to come to work every day knowing that what we do has a direct impact on people’s lives, with our core values guiding us every step of the way. Join us to invest in yourself, your career, and the financial world. The role: Responsible for physical security operations, investigations, executive protection support, incident response, and threat management functions across corporate environments and operational facilities. Serve as an operational leader within the broader Global Security & Investigations organization, responsible for managing day-to-day security operations, sensitive investigations, workplace violence prevention initiatives, executive protection assignments, and emergency response coordination while supporting enterprise security strategy and operational resilience. This role combines investigative expertise, operational leadership, and protective operations experience with strong judgment, crisis response capabilities, and cross-functional collaboration. The position assists with physical security operations including