Probe Equipment Shift Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a QEM PQE Quality engineer, you will be responsible to monitor and drive continuous improvement for the quality and reliability of cutting-edge memory/storage products manufactured in Fab10. Support the wafer manufacturing efforts for developing, validating, characterizing, and qualifying new products, enabling volume manufacturing with improved reliability performance to fulfill customer requirements. Leverage the knowledge of electrical operation and wafer fabrication technology of advanced NAND memory products to conduct root cause understanding for reliability failures or customer returns, and facilitate the implementation of required Fab specifications and documentation to ensure product quality meets or exceeds customer expectations. Job Responsibility: • Responsible for monitoring and improving Quality and Reliability for products out of Fab, including wafer level reliability sampling for Outgoing Quality Control. • Responsible to collect wafer level reliability data, manage various Reliability scorecard, and drive fab activities to improve Reliability performance (Extrinsic, Intrinsic, Process) for continuous improvement. • Ensure proper reliability and quality indicators including OQRM, Probe, Parame

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities Validation Execution Assist in executing Validation Runs on IQP/ETV materials under defined timelines, ensuring coverage completeness across MBIST and Native Mode flows. Support time-bound data crunching (log parsing, statistical summaries) and contribute to summary report preparation. Platform & Test Program Support Operate and debug programs on SM3/Cobra (MBIST) and Advantest V93K (Native) . Assist in hardware readiness: handler, socket, loadboard, and probe card setup. Technical Analysis & Simulation Validate high-speed I/O (>11 Gbps) and assist with eye diagram and signal integrity checks. Support Verilog simulation tasks (testbench execution, waveform review) to reproduce sightings and validate fixes. Data & Automation Develop basic scripts in Python for log parsing and data visualization. Maintain documentation in Confluence/Jira and version control in Git/Perforce. Debug & Collaboration Participate in root cause analysis sessions and assis

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we build the memory and storage that powers everything from massive data centers to the devices people rely on every day. Our design teams carry silicon all the way to systems—developing advanced memory architectures, shaping the products around them, and validating the solutions used across the globe. We take real ownership of the technology we create, and we're always pushing what memory can do! As a Staff Analog Design Engineer, you'll design and analyze the analog and digital circuits at the core of our memory products, directly shaping their performance, cost, and reliability. You'll work alongside Micron's design and verification teams around the world and support Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to build products that optimize manufacturing and keep customers coming back. It's a role where your circuit decisions show up in silicon that ships at scale. Responsibilities: Design, optimize, and verify block-level analog and mixed-signal circuits for DRAM Evaluate new circuit topologies to improve block PPAC Expand verification coverage to strengthen robustness and mass-production yield Partner with global design groups, guide layout through post-layout simulation, and support silicon-to-simulation correlation Apply agentic AI and automation tools to improve design quality and efficiency Minimum Qualifications: Bachelor's degree in Electrical Engineering with 6+ years of semicond

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Your responsibilities will include, but are not limited to, the following: Primarily focus on wafer matching including lot pairing and execution. Configure the bonding UI and continuously track development lots, including interpreting wafer matching outputs, executing wafer shuffling within the bonding UI, and monitoring subsequent wafer build and pairing. Apply AI-enabled ways of working to improve efficiency in wafer matching operations, lot tracking, data summarization, exception monitoring, and routine reporting where applicable. Assist Process Integration (PI) Engineers to coordinate and trouble shoot daily line issues such as disposition of line deviations and engineering job submissions for analysis. Assist in inline inspection and coordinate non-routine metro/RDA inspection on R&D experiments. Support process flow setup activities for production and the short loop flow. Extract, analyze, and summarize data from SWR and Conversion experiments in a report format and make recommendations to engineering based on the data. Manage wafer shipment logistics between fabs (swap lots and fab-to-fab offloads) for technology transfer and yield learning. Monitor key inline/probe/final parametric indices for any deviation an

About Druva Druva is the resilience foundation for the AI enterprise, helping organizations secure and recover from connected risk across data, cyber, identity, and AI. The Resilience Cloud is a fully managed, cloud-native SaaS platform that delivers air-gapped and immutable protection across cloud, SaaS, on-premises, endpoint, and edge environments. Powered by Dru MetaGraph, Druva’s graph-powered intelligence layer, the platform connects critical business context so customers can understand risk, respond faster, recover cleanly, and govern data with greater confidence. Trusted by nearly 7,500 customers, including 75 of the Fortune 500, Druva helps safeguard the critical information and systems businesses depend on in an increasingly connected world. Visit druva.com and follow us on LinkedIn , X and Facebook . The Role & The Team: We are looking for a talented, motivated, and quality-focused Senior Test Automation Engineer to design testing procedures for our software applications. The candidate will be responsible for analyzing the functionality of applications and designing automated tests to validate their stability and performance. They will have a technical background, a strong analytical thinker, and a proven ability to analyze complex solutions and define the appropriate test strategy. They will be a determined individual, who is confident to probe and question, and work with Developers and Product Owners to understand requirements and develop and maintain automated and manual tests. They will be responsible for active issue management in coordination within the team, communicating the cause, effect, and impact of those issues to the team, who can then prioritize appropriately. You will be responsible for coding, testing, and maintaining software systems, while mentoring and building the test capabilities of the agile teams. Reporting to the Director of Engineering, the candidate will recognize areas

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description: As a QEM PQE Electrical Failure Analysis (EFA) Engineer, you will be responsible for driving deep technical understanding and resolution of yield, quality, and reliability challenges for advanced NAND memory products manufactured in Fab10. You will support both new product introduction (NPI) and high-volume manufacturing (HVM) by performing die-level electrical analysis, failure mode construction, and innovative characterization to enable robust product qualification and continuous yield improvement. Leveraging strong knowledge in device physics, probe testing, and wafer fabrication processes, you will identify root causes of electrical failures and translate insights into actionable test, process, and design improvements to enhance product performance and outgoing quality. Job Responsibility: Perform electrical failure analysis (EFA) using bench characterization to identify failure mechanisms at die, circuit, and transistor levels Construct failure models and root cause understanding for yield excursion, reliability issues, and customer return cases <

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. This role is within Micron’s Package Development Engineering (PDE) group, a global organization with teams in the United States, Singapore, Malaysia, China, Taiwan, and India. As a Package Device Product Engineer (PDPE), you will support new DRAM, NAND, or managed NAND (mNAND) products by coordinating resources, test readiness, and analysis throughout the product lifecycle. You will perform data analysis and modeling, create and maintain root cause analysis documentation, analyze parametric, front-end (FE) probe, and back-end (BE) electrical test data, and respond to product failures. Responsibilities and Tasks Enable new BE test signals to capture assembly-related failures. Collaborate with Test Solution Engineering (TSE) and Product Engineering (PE) to ensure standardized test coverage and characterization, define characterization limits, and approve test-related changes. Develop and sustain new out-of-control action plans (OCAPs). Provide lot disposition recommendations based on parametric data observations when out-of-control (OOC) conditions are triggered. Ensure silicon and assembly processes meet product requirements by analyzin

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Summary As a Data Scientist at Micron, you will employ techniques drawn from mathematics, statistics, and information technology to uncover patterns in data, drive predictive models, and develop actionable solutions for advanced semiconductor manufacturing. Your primary focus will be to support Process Integration and Process Engineering teams to enhance product yield and improve process variation. You will interact closely with multi-functional process areas to solve manufacturing line problems and conduct root cause analysis. In this position, you will help develop software programs, algorithms, and automated processes to cleanse, integrate, and evaluate large datasets from multiple disparate sources—such as inline, param, and probe data—translating them into insights that directly improve process capability and device yield. Key Responsibilities Yield & Process Optimization: Collaborate with semiconductor manufacturing engineering teams to analyze inline/param/probe data to identify top yield detractors and drive continuous improvement. Data Pipeline & Automation: Extract, cleanse, and analyze datasets from SQL databases, sensor networks, and fabrication tool logs to support semiconductor manufacturing operati

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Your responsibilities will include, but are not limited to, the following: Assist Process Integration (PI) Engineers to coordinate and trouble shoot daily line issues such as disposition of line deviations and engineering job submissions for analysis. Assist in inline inspection and coordinate non-routine metro/RDA inspection on R&D experiments. Support process flow setup activities for production and the short loop flow. Extract, analyze, and summarize data from SWR and Conversion experiments in a report format and make recommendations to engineering based on the data. Manage wafer shipment logistics between fabs (swap lots and fab-to-fab offloads) for technology transfer and yield learning. Monitor and publish regular updates for priority and WIP lot movements. Monitor key inline/probe/final parametric indices for any deviation and to trigger first level of investigations promptly. Competent in the knowledge and expert usage of Micron’s systems to perform routine operational tasks effectively (Micron Central/DataNav/SPACE etc.). Own or contribute towards activities and projects that improve STC PI operationa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Senior Memory Design Engineer at Micron, you will have the outstanding opportunity to impact the future of memory technology! You will be working in an ambitious environment with a team of world-class engineers to build and analyze digital, analog, and mixed-signal circuits for advanced memory products. Our collaborative approach ensures flawless solutions and innovation, driving the success of future memory generations. Responsibilities Contribute to the development, optimization, and layout of Memory, Logic, and Analog circuits for next-generation memory products. Perform parasitic modeling and support build validation, reticle experiments, and required tape-out revisions. Coordinate and guide the layout process including floor-planning, placement, routing, and physical integration. Conduct circuit modeling and simulation using industry-standard tools to verify timing, functionality, and reliability. Collaborate across CAD, modeling, standards, and verification groups to align with best-known-methods and improve build quality. Partner with Probe, Test, Product Engineering, Assembly, Marketing, and Process Integration to ensure accurate manufacturability and product readiness. Support cross-team communication to promote standardization, consistency, and shared engineering success. Propel innovation through contributions to methodologies, architectures, and technologies for upcoming memory generations. Minimum Qualifications Bach

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Your responsibilities will include, but are not limited to, the following: Assist Process Integration (PI) Engineers to coordinate and trouble shoot daily line issues such as disposition of line deviations and engineering job submissions for analysis. Assist in inline inspection and coordinate non-routine metro/RDA inspection on R&D experiments. Support process flow setup activities for production and the short loop flow. Extract, analyze, and summarize data from SWR and Conversion experiments in a report format and make recommendations to engineering based on the data. Manage wafer shipment logistics between fabs (swap lots and fab-to-fab offloads) for technology transfer and yield learning. Monitor and publish regular updates for priority and WIP lot movements. Monitor key inline/probe/final parametric indices for any deviation and to trigger first level of investigations promptly. Competent in the knowledge and expert usage of Micron’s systems to perform routine operational tasks effectively (Micron Central/DataNav/SPACE etc.). Own or contribute towards activities and projects that impro

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Your responsibilities will include, but are not limited to, the following: Assist Process Integration (PI) Engineers to coordinate and trouble shoot daily line issues such as disposition of line deviations and engineering job submissions for analysis. Assist in inline inspection and coordinate non-routine metro/RDA inspection on R&D experiments. Support process flow setup activities for production and the short loop flow. Extract, analyze, and summarize data from SWR and Conversion experiments in a report format and make recommendations to engineering based on the data. Manage wafer shipment logistics between fabs (swap lots and fab-to-fab offloads) for technology transfer and yield learning. Monitor and publish regular updates for priority and WIP lot movements. Monitor key inline/probe/final parametric indices for any deviation and to trigger first level of investigations promptly. Competent in the knowledge and expert usage of Micron’s systems to perform routine operational tasks effectively (Micron Central/DataNav/SPACE etc.). Own or contribute towards activities and projects that improve STC PI operationa

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Your responsibilities will include, but are not limited to, the following: Assist Process Integration (PI) Engineers to coordinate and trouble shoot daily line issues such as disposition of line deviations and engineering job submissions for analysis. Assist in inline inspection and coordinate non-routine metro/RDA inspection on R&D experiments. Support process flow setup activities for production and the short loop flow. Extract, analyze, and summarize data from SWR and Conversion experiments in a report format and make recommendations to engineering based on the data. Manage wafer shipment logistics between fabs (swap lots and fab-to-fab offloads) for technology transfer and yield learning. Monitor and publish regular updates for priority and WIP lot movements. Monitor key inline/probe/final parametric indices for any deviation and to trigger first level of investigations promptly. Competent in the knowledge and expert usage of Micron’s systems to perform routine operational tasks effectively (Micron Central/DataNav/SPACE etc.). Own or contribute towards activities and projects that improve STC PI operationa

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. This is a hands-on technical role passionate about RTL build, IP integration, debugging, and pre/post-silicon support. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer