Semiconductor Equipment Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. • Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. • Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execu

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Responsibilities and Tasks: -Demonstrates thorough understanding of yield data analysis, Wafer Fabrication (Fab) processes and their common effects/signatures on yield/device. -Use knowledge of semiconductor device physics, electronics and semiconductor manufacturing process to explain and resolve yield issues using various statistical/data analysis tools. -Communicates the process/tool related yield toggles to the Fab process areas and support them in fixing the process/tool. -Should have excellent interaction with other internal Yield Enhancement (YE) groups and work to understand their constraints. -Create/participate in multi-area focus teams to solve sophisticated yield problems. -Publishes a clear Pareto of yield limiters on their specific part type. -Excellent verbal and written communication skills and the ability to present data in large meetings. -Support transfer of next generation technology from Research & Development to production Fab as and when necessary. Requirements: -Bachelor’s or advanced degree in Engineering or Science is required -Strong analytical, logical, and critical thinking skills -Effective communicator, able to collaborate across all levels -Growth mindset with a passion for continuou

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. Guide junior team-members in their execution of Sub block-level layouts & review their work Cont

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s advanced lithography and automation organization, where we tackle some of the most complex patterning challenges in semiconductor manufacturing. Our team works at the intersection of process technology, automation, and data, helping shape how next‑generation memory devices are built worldwide. If you enjoy solving hard technical problems and seeing your work scale globally, this is the place to do it! As a Photolithography Automation Engineer, you will play a key role in advancing overlay, critical dimension uniformity, and patterning through automation and data-driven solutions. This role offers hands-on technical impact today, while also influencing Micron’s long-term automation roadmap. You will collaborate closely with process engineers, automation experts, and vendors to bring new ideas from development into high-volume manufacturing. Responsibilities: Identify overlay, CD uniformity, and patterning challenges and define automation or data science solutions Execute and support automation projects in partnership with process development teams Collaborate with internal teams and vendors to improve photo automation systems Define hardware and software requirements for lithography automation solutions Document and standardize automation methods across technologies and global sites Minimum Qualifications: Bachelor’s degree in engineering, Physics, or a lithography-related field plus 5 years of relevant experience, or MS/PhD p

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. About the Role: Join our Product Engineering team to develop AI and Machine Learning solutions that transform semiconductor workflows. This role focuses on model development and agentic AI applications, enabling smarter testing, faster yield advancement, and engineering automation to improve cost, cycle time, and quality. This is a ground-breaking opportunity to work on modern technologies and make a significant impact in a world-class company! You will also train and guide Citizen Data Scientists (CDS or equivalent experience) within Product Engineering, helping them apply advanced ML techniques and analytics tools to gain domain-specific insights. Key Responsibilities: Machine Learning Development: Build predictive models for yield, test time, and reliability analysis using structured/tabular data Use advanced machine learning techniques to analyze complex datasets and generate actionable insights that improve manufacturing and operational performance Build and validate ML workflows for large-scale semiconductor datasets Agentic AI Solutions: Develop intelligent agents to automate engineering tasks (e.g., test program validation, yield analysis, report generation) Integra

Overview: The Insights product is an offering for Guidepoint's institutional investment and corporate clients, now in its 9 th year, that offers teleconferences, surveys, in-person events, and AI-facilitated data and content. The teleconferences live in an online library portal, which covers a wide of industries/topics that enables our clients to make informed decisions. All content features experts from Guidepoint’s proprietary global network and is conceptualized and hosted by former investment professionals (i.e. hedge fund analysts), sell-side equity research analysts, and industry professionals. This is a hybrid position based in our New York City office. What you'll do: Monitor a coverage universe of public companies within the global hardware and semiconductor sector by tracking earnings releases, investor presentations, SEC filings, sell-side research and industry news. Create and moderate teleconferences on timely topics featuring an expert from Guidepoint’s network with the goal of producing actionable insights for clients. Attend industry conferences to host client panels What you have: Bachelor’s degree or Master’s degree Minimum 10 years of sell-side or buy-side analyst experience Must follow bottoms-up, fundamental approach to investment research focusing on individual companies Has covered the Hardware and Semiconductor sector; candidates must be current on company/industry knowledge Ability to work in a fast-paced entrepreneurial environment Outgoing personality with the ability to speak with people at all professional levels Intellectual curiosity and desire to learn Effective time management and organizational skills Demonstrated ability to work both individually and as part of a team What We Offer: The annual salary range for this position is $210,000-$230,000. Additionally, this position is eligible for an annual discretionary bonus based on performance. You will also be eligible for the following benefits: 15

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. • Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execu

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Senior Emulation Engineer Location: India - Remote Job Description: At EnCharge AI, we are building the next generation of AI compute silicon — purpose-built for high-performance, low-power, and scalable AI inference. As an Emulation Engineer, you will play a critical role in validating complex AI accelerator architectures on emulation platforms before tape-out. This position is ideal for someone passionate about bridging the gap between hardware and software in fast-paced, deep tech environments. Responsibilities: • Set up and maintain Siemens Veloce emulation and prototyping platforms • Adapt SoC designs for Emulation and Prototyping • Develop and debug emulation testbenches and system-level environments • Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. • Collaborate with design and verification teams to isolate design issues and accelerate debug. • Optimize performance of the emulation workloads and reduce turnaround time. • Work with firmware/software teams to enable use of emulators for OS and driver testing. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 7+ years of SoC design experience. • Experience with emulation platforms (Veloce, Palladium, or ZeBu) and FPGA-based prototyping systems (proFPGA, HAPS, or Protium) • Experience with emula

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Physical Design Engineer (2-4 Years Experience) We are looking for a high-caliber Physical Design Engineer to join our fast-paced startup team. This role is designed for "top 1%" talent—engineers from tier-1 universities (IIT/NIT/BITS or equivalent) who possess a relentless "go-getter" attitude and the critical thinking skills required to solve complex, next-generation silicon challenges. If you are eager to move beyond standard digital flows into the future of AI-driven automation , this is your playground. Key Responsibilities End-to-End Ownership: Drive RTL-to-GDSII implementation, including floorplanning, placement, CTS, routing, and physical verification (LVS/DRC/ERC). Performance Optimization: Execute high-performance design closure focusing on PPA (Power, Performance, Area) targets in advanced process nodes ( 3nm or below) Static Timing Analysis (STA): Perform comprehensive timing closure, including signal integrity, crosstalk analysis, and CPPR (Common Path Pessimism Removal) optimization. Power Integrity: Conduct IR-drop analysis (Static/Dynamic) and EM (Electromigration) checks to ensure robust power delivery. Innovation: Develop and integrate AI/ML-based automation scripts to optimize the physical design flow and reduce turnaround time. Qualifications &am

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 43 years, Micron Technology, Inc. has advanced the world’s most innovative memory and semiconductor technologies. As an HBM Memory Design Engineer within the HBM Architecture Team, you will design, simulate, and optimize digital and analog DRAM circuits for next‑generation high‑bandwidth memory products. You will evaluate block‑level and full‑chip functionality, solve complex challenges in building, and collaborate with a distributed team to deliver highly reliable, industry‑leading HBM solutions. This role provides the opportunity to contribute to groundbreaking DRAM design, TSV‑based 3D integration, and high‑speed mixed‑signal architectures supporting Machine Learning and AI applications. Responsibilities Design and analyze digital, analog, and mixed‑signal circuits for HBM DRAM products. Perform schematic entry, simulation, and optimization of DRAM blocks including data path, ECC, command control, and clocking circuits. Evaluate full‑chip and block‑level functionality and deliver solutions ensuring functional accuracy. Conduct pathfinding and feasibility studies for next‑generation HBM architectures. Optimize circuit timing, area, power, and complexity across high‑speed DRAM designs. Support design floor planning, layout reviews, and cross‑domain integration of memory, logic, and analog circuits. Collaborate with global engineering teams to drive innovation and support vertical integration across design

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a highly skilled and experienced Engineer to lead post-silicon power characterization and correlation activities for cutting-edge semiconductor products. In this role, you will be responsible for developing and executing detailed power measurement strategies on silicon, correlating results with pre-silicon models, and driving improvements across power architecture, design, and modeling methodologies. You will serve as a key technical leader, interfacing across design, architecture, validation, and systems teams to ensure silicon meets power and performance specifications under all operating conditions. This role is hybrid, based out of Toronto, ON or Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are A Principal-level engineer with 8+ years in silicon power analysis and characterization, and a Master’s or PhD in EE, CE, or related field. Deep understanding of digital and mixed-signal power domains, including DVFS, leakage vs. dynamic power, and power gating. Highly proficient in lab-based power measurement using oscilloscopes, current probes, power analyzers, and SMUs, plus Python/Perl/MATLAB

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Welcome! Are you ready to be at the forefront of ground breaking Engineering within the semiconductor industry?! Micron Technology, Inc., a global leader in memory and storage solutions, is seeking a dedicated and experienced Senior Engineer to join our Chemical team within the Global Facilities Engineering department. In this crucial role, you will play a vital part in providing high-quality Engineering services and support for the planning, design, construction, operation, and maintenance of our subject area specific Facilities systems across our Semiconductor Manufacturing sites worldwide for Chemical systems and Slurry systems. As a Senior Engineer, Chemical for the Global Facilities Engineering department at Micron Technology, Inc., you will be responsible to provide high quality Engineering services and support for the planning, design, construction, operation, and maintenance of your discipline specific Facilities systems in support of the Semiconductor Manufacturing sites across the Micron Global Manufacturing Network – for Chemical systems and Slurry systems. In this role, you will support the Facilities Teams and Manufacturing sites across the network as the Technical Subject Matter Expert through all phases of design, construction, installation, start-up, operations and maintenance with focus and emphasis on Global Standardization and Alignment, Innovation, Reliability and Performance, and Sustainability. Responsibilities: Technical Support, Leadership, a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As the Gas Engineer for the Global Facilities & Construction North Asia Regional Department at Micron Technology, you will play an instrumental role in ensuring the latest planning, build, construction, and maintenance of Bulk and Specialty Gas systems across our semiconductor manufacturing sites in China, Taiwan, and Japan. This opportunity is groundbreaking because you will lead the standardization, innovation, and sustainability efforts in a modern industry! Responsibilities and Tasks Offer Technical Support, Direction, and Expertise Offer consultation and support to Site Facilities & Manufacturing teams in North Asia as the Technical Field Subject Matter Expert. Collaborate with internal partners including Technology Development Team, Procurement, Finance, and Legal. Develop, review, and maintain Micron system standards, specifications, and Established Procedures (EPs). Ensure standardization and alignment across the North Asia network for engineering concepts, construction projects, and operations practices. Analyze system builds for performance improvements, efficiency gains, and cost savings. Support sites with problem analysis using standard tools and methodologies. Benchmark engineering guidelines and BKMs within and outside Micron. Stay updated on industry trends, technological advances, and sustainability initiatives. Provide Build and Construction Project Support, Leadership, and Expertise Supp

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff/Senior Staff Physical Design Floorplan & PDN Lead Experience: 10–14 Years Location: Bangalore/2 days to work Department: RTL-to-GDSII / Physical Implementation Role Overview We are seeking a high-caliber Staff or Senior Staff Physical Design Engineer with a specialized mastery of Floorplanning and Power Delivery Network (PDN) design. You won’t just be pushing buttons; you will be the architectural bridge between RTL/Systems and the final GDSII. This role requires a visionary who understands how a single floorplan decision ripples through the entire PPA (Power, Performance, Area) spectrum. As a technical lead, you will own the chip-top floorplan for complex, large-scale SoCs or Sub-chips, driving strategies that balance aggressive performance targets with robust power integrity. Key Responsibilities Architectural Floorplanning: Lead chip-level floorplanning, including macro placement, pin assignment, and partition definition for multi-million gate designs. Strategic PDN Design: Architect and implement complex Power Delivery Networks. You will define the metal stack usage and grid density to support high-performance cores while minimizing routing congestion. EMIR Mastery: Perform exhaustive IR-drop (Static/Dynamic) and Electromigration (EM) analysis. You must be able to diagnose root causes and propose ar