Senior Memory Circuit Design Verification Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Mask Development department in Micron’s Technology Development organization delivers reticle solutions that help shape next-gen memory and storage products in the evolving global technology landscape. This team works at the intersection of advanced equipment, materials science, and precision manufacturing. If you enjoy solving complex problems, collaborating with other subject-matter experts and department leaders, and seeing your direct impacts on product quality, you’ll feel at home here! Position Overview: Micron is seeking a highly experienced Resolution Enhancement Techniques (RET) Engineer to join the AMD team at Micron. At the Senior Member of Technical Staff level, our ideal candidate is a master in their field and has a history of innovation and driving technical direction in the industry. This role will focus on developing and optimizing RET and Optical Proximity Correction (OPC) solutions that enable high-fidelity wafer patterning for advanced memory technologies. This role will partner with a variety of teams to develop innovative reticle solutions, improve tapeout methodologies, and resolve complex patterning challenges across both R&D and HVM environments. We are looking for an ambitious and goals-centric individual to help drive groundbreaking solutions that maintain Micron’s competitive advantage. Responsibilities: Drive a steady stream of sophisticated projects with built-in contingency plans related to mask development, lithography optimization, and tapeout flow

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As a EE senior Manager, you will be responsible for the strategic ,tactical planning and execution to meet the business plan within budget, this includes but not limited to short and mid-term capacity planning, automation enablement, equipment performance continual improvement, human resources organization, management, technical and leadership development. Lead the adoption of AI-enabled engineering and management practices to improve equipment reliability, manufacturing efficiency, resource optimization, and business performance. Drive the integration of AI, advanced analytics, automation, and digital solutions into engineering workflows, problem solving, capacity planning, maintenance strategies, and operational decision making. Identify and prioritize AI use cases that deliver measurable business impact, promote the effective use of Microsoft Copilot and approved AI tools across the organization, and develop team capabilities in AI-assisted engineering, data-driven decision making, and continuous improvement to support Micron's AI transformation journey. Responsibilities and Tasks Work with Equipment team to drive equipment performance continual improvements. Work with the PEE and IE to assess and audit the capacity of each workstation in the strategic and tactical timeframe, identify increased throughput opportunities as well as risks to meet Cycle Time and Business Plan goals. Develop action plans to maximize opportunities and mitigate risks.</p

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a strong, well rounded leader who works well cross functionality to shape and execute our strategic efforts around M&A, Venture Capital, and Corporate Business Development activities: Responsibilities Drive M&A and Venture Capital strategy in partnership with senior corporate and subsidiary leadership, including opportunity identification and prioritization. Lead sourcing, evaluation, and due‑diligence efforts for M&A, VC, and partnership opportunities, assessing strategic fit, financial value, and integration requirements. Manage cross‑functional teams through diligence, deal execution, operational assessment, and post‑deal integration planning. Build and maintain strong relationships with target company executives while regularly scanning markets for new business and technology opportunities. Prepare acquisition proposals, validate financial models, and deliver strategic recommendations and presentations to executives and key collaborators. Minimum Qualifications Bachelor’s degree in a STEM field and 10&#43; years of progressive experience in M&A, Venture Capital, financial modeling, deal structuring, negotiation, and strategy. Demonstrated experience leading transaction processes, conducting due diligence, and performing independent business and strategic assessments. Strong analytical, valuation, and financial modeling capability with the ability to ma

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff Engineer: STA Methodology & Sign-off Lead We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges. This is a critical role for a forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out. The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes. Flow Development & Left-Shift Automation: Architect, deploy, and maintain adva

We are expanding our agentic AI capability and are looking for an AI Engineer to join the team. You will work alongside senior engineers to build and maintain AI systems — contributing to agentic pipelines, retrieval infrastructure, and the integrations that tie these systems together. This is a hands-on implementation role with real ownership of components. You will grow your skills in a fast-moving AI practice, working on production systems that directly affect client outcomes. What This Involves: Build and maintain agentic pipelines and workflows under the guidance of senior engineers: tool use, orchestration, and multi-step reasoning. Implement and tune RAG pipelines — including embedding, chunking strategies, vector retrieval, and retrieval evaluation. Contribute to memory and context layer components: integrating vector databases, supporting knowledge graph pipelines, and helping maintain state management across agentic systems. Write clean, well-tested Python code and participate in code reviews. Debug and improve existing AI systems based on evaluation results and production feedback. Collaborate with data engineers and domain experts to integrate AI components with upstream data sources and downstream applications. Document implementations clearly and contribute to shared internal tooling. Requirements: 2–4 years of software or ML engineering experience, with at least 1 year working with LLMs or AI systems in a professional setting. Working knowledge of LLM APIs (OpenAI, Anthropic, or similar) and at least one agentic or RAG framework (LangChain, LlamaIndex, or equivalent). Solid Python skills and comfort with software engineering basics: version control, testing, REST APIs. Familiarity with vector databases or embedding-based search. Curiosity about agentic AI — you follow developments in the space and are eager to apply new techniques. Excellent communication and collaboration skills — comfortable working across cross-functional and client-facing te

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a US Expansion Planning Engineer, you will be a key contact in preparing for production in a new high volume memory manufacturing facility in Boise, Idaho, calculating and presenting capital impacts of processes that will be introduced at the site to senior leaders in manufacturing and R&D. Innovation is highly valued at Micron. In this role, you will have the opportunity to develop new visualization and data driven tools to expedite, optimize and refine the fab planning and reporting processes used to prepare, ramp, and operate the site. Successfully partnering with supply chain, finance, engineering, procurement, production, and R&D, you will connect the business in driving execution of manufacturing, including long term capacity, capital planning and cost savings, for the operation. The ability to understand and efficiently communicate capital impacts of manufacturing changes is essential. Every day, our team has the opportunity to provide recommendations which will transform the future of memory manufacturing through data analysis and a growth mindset. Are you ready to meet the challenge? Your responsibilities will include, but are not limited to: Collaborate with partners to drive future tool and process roadmaps, and calculate network capacity impacts of process changes Complete financial analyses before new capital equipment is purchased including metrics optimization, process flexibility, capacity sharing and equipment repurpose Handle site tool utiliza

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is seeking a highly motivated Senior Data Science & Product Yield Analytics Engineer to join the Product Yield & Analytic (PYA) organization. This role focuses on applying data science, software engineering, and advanced analytics to semiconductor manufacturing data, with a strong emphasis on Improved Software for Defect Analysis (ESDA) and Electrical Failure Analysis bench testing systems used companywide. In this position, you will employ techniques drawn from statistics, machine learning, semiconductor physics, and large‑scale data engineering to uncover patterns, build predictive models, and develop actionable insights that drive yield, quality, and reliability improvements across Micron’s memory products. You will work closely with Data Scientists, Data Engineers, Product Engineers, Build teams, Yield Enhancement, RDA, Failure Analysis, and IT teams across global sites to develop and expand ESDA capabilities and analytics platforms that directly support manufacturing and product development. Responsibilities: Expand and enhance ESDA capabilities to improve yield, quality, and product reliability. Develop yield, defect matching, and modeling methods to accelerate manufacturing feedback to RDA and YE teams. Create and maintain engineering software tools for ESDA analytics and product line monitoring. Collaborate with design, failure analysis, and product teams to optimize redundancy, compression, and defect analysis methodologies. Support next-ge

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Role Summary The PDE PCS IIoT Senior Manager is responsible for leading the validation, industrialization, and high-volume manufacturing (HVM) enablement of Industrial IoT solutions across the enterprise. This role ensures that IIoT solutions developed through early pathfinding and solution development phases are scalable, robust, compliant, and standardized for global deployment. The position plays a critical governance role across the IIoT lifecycle—driving design-for-scale alignment, enforcing validation rigor, and enabling consistent fanout across sites. The role partners closely with APTD IIoT, site engineering teams, and central functions to deliver production-grade IIoT capabilities that achieve yield, productivity, and operational performance targets. Key Responsibilities 1. IIoT Validation and Industrialization Leadership Own end-to-end IIoT solution validation from pilot through industrial deployment. Ensure solutions are robust, scalable, and meet defined performance targets (e.g., DOC, latency, reliability). Establish and enforce validation frameworks including: Data quality and integrity checks Algorithm robustness and drift validation False positive/false negative performance thresholds Drive cybersecurity, compliance, and enterprise governance sign-off prior to deployment. 2. HVM Fanout and Standardization Lead SOAK fanout governance and ensure control

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As Front End Central Product Integration, CPIE ( Central Product Integration Engineering) HBM (High Bandwidth Memory) PI Principal Engineer/Senior Manager at Micron Technology, Inc, you will be responsible for providing leadership to the global Micron network to drive leading edge HBM Product yield, quality improvement, new product introduction (NPI) through technical expertise, business process management and project execution, collaborating with Japan, Taiwan, Singapore and US team, driving product maturity within a defined schedule while maintaining the highest standards of quality. Responsibilities and Tasks STRATEGIC LEADERSHIP Work with FAB to drive for best-in-class (BIC) Yield ramping. Work with key business partners to develop strategic Process Integration tools, systems, methodologies, capabilities and roadmaps. Ensure such support and roadmaps meet business expectations to enable achievement of strategic objectives and Micron’s business plan. Create an environment with your group that encourages innovation and technical leadership. TACTICAL LEADERSHIP Conduct ongoing metrics reviews of critical group deliverables to business. Ensure work reviews are conduct

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Sustainability Operations (Senior/Staff) Program Manager Job Summary Micron Technology’s vision is to change the way the world accesses information, enriching life. We show dedication to people, innovation, tenacity, collaboration, and customer focus. This dedication allows us to be a global leader in memory and storage solutions. This means conducting business with integrity, accountability, and professionalism while supporting our global community. Micron, one of the world’s largest semiconductor companies, recognizes its environmental impact. We take proactive steps to protect the environment. Our goal is to align emissions with the Paris Agreement and keep warming below 2 degrees Celsius. We support the United Nations Sustainable Development Goal 13 on Climate Action. We aim to reach net-zero greenhouse gas emissions in our operations (scope 1) and purchased energy (scope 2) by 2050. We plan a 42% absolute reduction in scope 1 emissions by calendar year 2030 (CY30) compared to the CY20 baseline. We are also working toward 75% water conservation through reuse, recycling, and restoration by CY30. Micron has committed to investing approximately $1 billion by 2028 to support these environmental goals. About the Role The Global Sustainability Operations (Senior/Staff) Program Manager will direct the strategy, delivery, and governance of sustainability initiatives, prioritizing on water conservation and sustainability cost management across operating locations. This role is responsible for conve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As a senior Manager, you will be responsible for the strategic ,tactical planning and execution to meet the business plan within budget, this includes but not limited to short and mid-term capacity planning, automation enablement, equipment performance continual improvement, human resources organization, management, technical and leadership development. Responsibilities and Tasks Work with Equipment team to drive equipment performance continual improvements. Work with the PEE and IE to assess and audit the capacity of each workstation in the strategic and tactical timeframe, identify increased throughput opportunities as well as risks to meet Cycle Time and Business Plan goals. Develop action plans to maximize opportunities and mitigate risks. Work with PIE and SIC team on new technology node and new part types line readiness matrix. Work with HVM/ PEE and EE on area constraint management/improvements (dynamic constraints) . Work with OI team on area MAS scheduling, automation, line management systems and successfully roll out to the shift team. Work with Engineering team on tool qualification, release and install requirements, and maintenance priorities. Work with PIE yield improvement and quality. Work closely with other departments to meet the needs of the Fab and build strong peer relationships. Develop organization resource plans, training plans and business processes within organization operation to meet Business Plan. <p style="text-alig

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) team at Micron drives the technologies that enable the AI era. We work hands‑on with global R&D, suppliers, and manufacturing teams to turn breakthrough ideas into production‑ready solutions. Our work sits at the intersection of innovation, scale, and real‑world impact—and collaboration is how we win. Position Overview: Artificial intelligence is transforming the world, and High Bandwidth Memory (HBM) is at the center of that transformation. As a Senior or Staff Engineer on the Dry Etch R&D team, you will play a key role in developing and scaling plasma‑based etch processes that enable next‑generation packaging technologies. This role offers deep technical ownership, broad cross‑functional collaboration, and the opportunity to influence long‑term technology roadmaps from early research through high‑volume manufacturing. Responsibilities: Develop and optimize dry etch process modules to meet performance, yield, and reliability requirements for advanced packaging products Drive process capability, cost, and variability improvements using data‑driven experimentation and equipment innovation Collaborate closely with process integration and adjacent process teams including Wet Etch, Films, Lithography, CMP, Wafer Trim, and Bonding Perform root‑cause and failure‑mode analysis a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description As a senior Manager, you will be responsible for the strategic ,tactical planning and execution to meet the business plan within budget, this includes but not limited to short and mid-term capacity planning, automation enablement, equipment performance continual improvement, human resources organization, management, technical and leadership development. Responsibilities and Tasks Work with Equipment team to drive equipment performance continual improvements. Work with the PEE and IE to assess and audit the capacity of each workstation in the strategic and tactical timeframe, identify increased throughput opportunities as well as risks to meet Cycle Time and Business Plan goals. Develop action plans to maximize opportunities and mitigate risks. Work with PIE and SIC team on new technology node and new part types line readiness matrix. Work with HVM/ADTT PEE and EE on area constraint management/improvements (dynamic constraints) . Work with OI team on area MAS scheduling, automation, line management systems and successfully roll out to the shift team. Work with Engineering team on tool qualification, release and install requirements, and maintenance priorities. Work with PIE yield improvement and quality. Work closely with other departments to meet the needs of the Fab and build strong peer relationships. Develop organization resource plans, training plans and business processes within organization operation to meet Business Plan. <p style="text-

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary At Micron Technology, we are looking for a Senior RTL Engineer to build and develop DRAM digital and mixed-signal blocks for advanced memory products. In this role, you will support the RTL lifecycle from specification and implementation to signoff. You will collaborate with multi-functional teams to develop high-quality builds that meet power, performance, and area (PPA) targets. This position is based in Boise, Idaho, within a collaborative and innovative engineering environment. Responsibilities Contribute to RTL build of digital and mixed-signal components for DRAM using RTL-to-GDS flows. Implement and document high-performance, power- and area-efficient RTL designs meeting product specifications. Perform front-end quality checks including lint, CDC/RDC, synthesis, UPF, and timing QoR. Collaborate closely with physical design and implementation teams to achieve timing closure and PPA goals. Apply power-, clock-, and implementation-aware RTL design practices to minimize silicon risk. Minimum Qualifications Master’s degree in Electrical Engineering with 4&#43; years of experience, or Bachelor’s degree with 5&#43; years of pre-silicon RTL design experience. Demonstrated experience developing RTL for complex digital IP from specification through implementation handoff. Hands-on experience with ASIC low-power design methodologies, including UPF-based power intent and CDC/RDC analysis. Strong knowledge of ASIC design flows, including RTL design, logi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc