Si Simulation Engineer Jobs

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities Perform pre-layout and post-layout signal integrity simulation for high-speed interfaces, including DDR4/DDR5, PCIe Gen3–Gen5, and 100G/400G/800G Ethernet. Evaluate channel loss, PCB material, stack-up, IC placement, and routing constraints during the early design stage. Build and analyze end-to-end channel models, including PCB traces, vias, connectors, cables, packages, and IC models. Optimize high-speed channel structures, including vias, anti-pads, connector launches, cables, and routing topology. Analyze insertion loss, return loss, crosstalk, impedance discontinuity, jitter, eye diagram, and BER performance. Define PCB layout guidelines and routing constraints for high-speed interfaces. Work with EE, layout, mechanical, vendor, and validation teams to review designs and resolve SI issues. Support simulation-to-measur

About the Team Our Robotics team is focused on unlocking general-purpose robotics and advancing toward AGI-level intelligence in dynamic, real-world environments. Working across the full model and systems stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the physical constraints of real-world systems to improve people’s lives. About the Role We are looking for a PCB Layout Engineer to design high-density electronics for next-generation robotic systems. You will own PCB layout from floor planning through fabrication release, working closely with electrical, SI/PI, mechanical, and manufacturing teams. This role is based in San Francisco and requires in-person presence four days per week. In this role, you will: Own PCB layout, component placement, routing, and fabrication release for complex robotic systems. Collaborate with SI/PI engineers to refine layouts based on simulation results. Implement high-speed routing, controlled impedance, power distribution, decoupling, grounding, EMI/EMC, thermal, and mechanical-integration requirements. Work directly with fabricators and assembly partners to define stack-ups, establish design rules, drive DFM/DFA/DFT reviews, and close findings before release. Prepare fabrication and assembly documentation, including drawings, ODB++, drill files, stack-up tables, and manufacturing notes. Inspect newly received PCBAs and particip

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job responsibilities: Technical Expertise : Should possess very strong PCB technical knowledge on high-speed layouts with HDI technology and have very good experience with DDR4/DDR5, PCIe4/5/6, ONFI4.0/ONFI5.0, SMBus and I2C interfaces placement and routing consideration. Strong design experience of power delivery network routing using PMIC devices. Design and Development: Lead the design and development of, SSD's drive PCB layouts, EDSFF (E3.S, E1.L, E3.L) and U.2 form factors, daughter cards, Evaluation and Test PCB layouts. Quality Assurance: Ensure all designs comply with industry standards (IPC) and regulatory requirements (UL, IEC). Problem

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define what is possible at the limits of speed and scale. Our architecture team evaluates future interfaces early, using data‑driven analysis to guide product and IO strategy. This role focuses on early‑phase SI architecture exploration. You will independently model, simulate, and assess high‑speed interfaces and translate findings into clear architectural intent and requirements. This role uses AI for work optimization. Responsibilities: Define SI architectural strategies for high‑speed memory and system interfaces Perform early feasibility and scaling analysis for future data rates Build hands‑on channel models across package, board, and system Drive end‑to‑end SI co‑design with IO, package, and system architects Translate SI insights into electrical requirements and architectural constraints Minimum Qualifications: Bachelor’s degree or equivalent practical experience in Electrical Engineering or related field 10+ years of experience in signal integrity or high‑speed interface de

We are seeking a highly skilled and visionary Staff Signal and Power Integrity (SI/PI) Engineer to join our advanced hardware engineering team. In this role, you will be the definitive technical expert responsible for ensuring the signal quality, timing, and power delivery robustness of our most complex, next-generation robotaxi electronic systems. As a technical pillar within the organization, you will define overarching SI/PI architectures, establish company-wide simulation methodologies, guide electrical design and layout teams, and own the end-to-end sign-off for cutting-edge high-speed interfaces. In This Role, You Will Lead the SI/PI architecture and define constraints for next-generation, high-complexity, high-density printed circuit boards (PCBs) and overall system design. Collaborate at an architectural level with hardware design, silicon vendors, PCB layout, and mechanical engineering teams to define layer stack-ups, routing strategies, component placement, and power delivery architectures. Analyze, optimize, and sign off on advanced high-speed serial links (PCIe, Ethernet, MIPI, GMSL) and memory interfaces (LPDDR). Provide expert-level design guidance and validation for automotive-specific communication and audio protocols (A2B). Architect and conduct comprehensive Power Delivery Network (PDN) analysis, including DC IR drop, AC impedance modeling, and transient response analysis to ensure stable power delivery across

Job Details: Job Description: The world is transforming and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth. The E-Core CPU team is a CPU Core development team in Guadalajara, Mexico. We believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we welcome you to join us, to do something wonderful. The focus of this role is to be part of a team of pre-silicon verification engineers to verify new and existing features for Intel's next generation CPU IP resulting in bug free final design. You will be responsible for exhaustively validating the RTL implementation of new architecture and microarchitecture capabilities using a combination of standalone and top-level test environments as well as formal verification. This team is responsible to ensure the highest quality of Intel's CPU designs, in a dynamic cross-team environment. Role responsibilities include although not limited to: Developing pre-Si validation test plans and test scenarios to prove the correctness of the design.</li

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI a

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC

Guidance & Control Engineer (Associate or Experienced) Company: The Boeing Company The Boeing Company is actively seeking an Associate or Experienced Guidance and Control (G&C) Engineer (Level 2 or 3) in St. Charles, Missouri to support our Weapons programs. Within the Boeing Defense, Space & Security (BDS) Space, Intelligence & Weapon Systems (SI&WS) organization, the Weapons business is growing with multiple ongoing production and development programs serving the US Air Force, US Navy, US Army, and international customers. Selected candidates will work a wide range of Weapons programs that will provide state of the art G&C algorithms, performance analysis and simulation solutions to our customers, and will have visibility across the Boeing enterprise into modern G&C and simulation development methods. Come join the Boeing Team! Position Responsibilities: Gather and define system level requirements for Guidance and Control systems or missions/trajectories Perform design & analysis of Guidance and Control systems, simulations, models & tools Support design reviews, analyses, simulations and component / system testing to ensure delivery of products that meet or exceed customer requirem

1891 Signal Integrity Measurement Engineer Location: Austin About the Role Validate signal integrity (SI) and power integrity (PI) for advanced compute platforms, focusing on hands-on measurement, electrical compliance, troubleshooting, and simulation correlation. Key Responsibilities Develop measurement plans and design of experiments (DOE) for board-to-board, cable, backplane, blade-, and rack-level interconnects. Measure scattering parameters (S-parameters), insertion loss, return loss, impedance, crosstalk, eye diagrams, jitter, timing margins, and bit error rates. Design printed circuit board (PCB) test fixtures; perform calibration, de-embedding, and electrical compliance testing against interface specifications and customer requirements. Correlate measurements with simulations and troubleshoot issues with silicon, package, board, and system teams, interconnect vendors, and original design manufacturers (ODMs). Prepare validation and compliance reports covering methods, pass/fail results, performance margins, findings, and recommendations. Required Qualifications Hands-on expertise with vector network analyzers (VNAs), including performance network analyzers (PNAs); time-domain reflectometers (TDRs); bit error rate testers (BERTs); and high-speed oscilloscopes. Strong SI/PI fundamentals and experience with fixture characterization, repeatable measurements, DOE, and electrical compliance testing. Strong written and verbal communication skills for technical r

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead system signal integrity (SI) design for AI supercomputer product in the data center application. Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity Perform simulation and modeling to identify and troubleshoot signal integrity issues Lead system interconnect design, bring up and qualification As the scope of

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. THE ROLE We are seeking a highly motivated Hardware Signal Integrity (SI) Engineer for Everpure’s Datastore team. In this role, you will own high-speed signal integrity analysis, simulation, and measurement for enterprise SSD platforms. WHAT YOU'LL DO Own signal integrity analysis for SSD hardware from architecture through production. Drive board-level SI decisions, including: PCB material selection, via structures, loss tradeoffs, stackup definition and channel optimization. Perform SI simulations including: Insertion loss (IL), return loss (RL), crosstalk, TDR / impedance profiles. Lead TDR and S-parameter measurements, including: measurement setup, Calibration and de-embedding. Perform 3D-EM extraction and simulation for vias, connectors, and complex channel structures. Correlate simulation results with lab measurements to refine models and design assumptions. Use and customize IBIS and IBIS-AMI models for PCIe, NAND and DDR chan

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. The role We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry. Pure builds the industry’s most innovative, high-performance, energy-efficient and TCO-optimised storage solution. This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us. We are seeking a highly motivated Hardware Signal Integrity (SI) Engineer for Pure’s Datastore team. In this role, you will own high-speed signal integrity analysis, simulation, and measurement for enterprise SSD platforms. WHAT YOU'LL DO Own signal integrity analysis for SSD hardware from architecture through production. Drive board-level SI decisions, including: PCB material selection, via structures, loss tradeoffs, stac

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the Compute and Memory Business Unit (CMBU), driving the innovation behind Micron's next generation DRAM solutions for AI, data center, and client computing platforms. Our team collaborates across product architecture, design, validation, and system engineering to solve complex challenges in bandwidth, power, reliability, and scalability. Together, we help shape the future of memory technology for the world's most demanding compute environments. As a Product Architecture Engineer focused on Signal Integrity (SI) and Power Integrity (PI), you will define the electrical architecture that enables next-generation DRAM products. This highly visible role combines deep technical expertise with system-level thinking to influence product roadmaps, guide design decisions, and partner with industry-leading ecosystem stakeholders. Your work will help deliver memory solutions that power tomorrow's AI and high-performance computing platforms. Responsibilities: Lead SI/PI architecture pathfinding for next-generation DRAM products across

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Seeking a self-motivated, team-oriented board design & validation engineer to develop Micron’s next generation Solid State Drive (SSD) products. This position requires experience in hardware design, signal integrity and power supply design and characterization. This would include modeling and simulation for high speed signaling implementations and power supply design including power distribution network (PDN) simulations. Job responsibilities: Technical Expertise : Candidate should have in depth knowledge on PCIe interface Gen5 & Gen6, PCIe Base and CEM specs, LPDDR4/5, NAND memories, ONFI interface (preferred) Strong knowledge on DC-DC converters, Buck and Boost, PMIC, Power Loss Protection (PLP), LDO, Load Switch devices A thorough understanding of Signal Integrity (SI), Power Integrity (PI), and Electromagnetic Compatibility (EMC) requirements is very much important. Hands on experience in performing measurements using low- and high-end Oscilloscopes,