Snr Specialist Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron Technology is the world leader in memory and storage solutions with vision of transforming how the world uses information to enrich life for all. As the Operations Central Team (OCT) Pump, Abatement and Chiller (PAC) Senior Manager at Micron Technology, Inc., you will be responsible for leading Front-End Manufacturing PAC strategic objectives to achieve the Best in Class (BIC) performance across network and industry. You will also be responsible for mentoring and building growth mindset, facilitate and drive improvement on Micron PAC engineering globally, driving global business processes, and enabling the leverage of world-wide resources to deliver industry benchmark methods. You are encouraged to work closely with global peer groups to identify areas of opportunities to improve PAC performance. Micron is attracting the diversified and talented candidate to build innovative solution for all aspects. Responsibilities and Task: Develop and manage PAC engineering strategy and direction to meet PAC strategic objectives for key pillars (People, Safety & Sustainability, Cost, Speed, Scale and Quality) Create, align and drive compliance in global PAC BKM and business process. Collaborate with global peer groups from sites, Technology Development (TD), central teams and suppliers to execute strategic objectives to achieve Best-in-Class (BIC) performance. Define, prioritize and manage resources for the PAC engineering with metrics across key projects based on strategic objectives. Drive

Snr/Staff Equipment Development Engineer (APTD) — Fab 10A, Singapore. Apply via Workday.

Snr Engineer/Engineer FE Global PLN Strategic & Modeling — Fab 10A, Singapore. Apply via Workday.

Global Layout Snr/ Staff Engineer — Taichung - Fab 16, Taiwan. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As a Central Planning Modeling Engineer, you will be a central contact for the manufacturing network, calculating and presenting capital impact of process changes to senior leaders in Manufacturing and R&D . You will be responsible for connecting many parts of the business in order to drive the execution of manufacturing and cost saving processes, including supply change, finance, engineering, procurement, production and planning. Innovation is highly valued at Micron, and you will have the opportunity to develop new tools to expedite, optimize and refine the planning and reporting processed used across the network. The ability to understand and effectively communicate the capital and operational impacts of manufacturing changes is important. Attention to detail and ability to work in where information is ambiguous will be extremely valuable Responsibilities Lead network tool utilizations strategies and benchmark performance to optimize the company’s deployed capital Lead and communicate improvement and implementation plan to all relevant levels and functions in Manufacturing Optimize capacity of install equipment and lead sites and tool level optimizatio

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations). Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data Support design rule checking (DRC) of both base and mask layers and interface with physical verification team. Define algorithms for generation of mask data from drawn base layer data. Involve projects across multi-disciplinary teams focusing on layout and mask generation issues About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of hig

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. We have an opening for Yield Analysis Engineer for NAND Technology Department in Singapore. We are looking for candidate that is passionate to innovate in data analytics, and curious to ask "what, how and why"? In this role you will be responsible for providing key feedback and direction on yield improvement activity for NAND memory technology! This role requires a high degree of collaboration across virtually all company functions, up to and including the Executive level. As Yield Analysis Engineer , you will be responsible for developing innovative NAND product technologies, define, and execute various effective actions to enable solutions to improve yield, quality, reliability, and hit key milestones & achieve the required performance within committed timelines. Your responsibilities will include, but are not limited to, the following: Discover yield issues in NAND development and identify unique metric or combination of metrics, such as wafer/dice/tile shading, ECATS or other custom metric for issues quantification Interact with process area, process integration, yield, failure analysis, product engineering, design, and layout teams to drive clear definition of yield, cell, CMOS,

Global Facilities Document Control Snr Engineer — Hiroshima - Fab 15, Japan. Apply via Workday.

FE CPIE RDA Defect Engineering Snr Engineer/Principal Engineer — Taichung - Fab 16, Taiwan. Apply via Workday.

Frontend Central Product Integration Engineering (CPIE) Engineer/Snr Engineer — Fab 10A, Singapore. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Micron Global Quality FE Central Wafer Quality (SNR) Engineer, you will be a member of the worldwide quality team, responsible for driving quality and reliability initiatives into FE MFG network for compute and mobile products, including LPDDR for critical customer AI applications and support fab expansion quality equivalency governance. You will work closely with DEG PE/PYE/GQ, FE fab teams and Central PIE to establish BKMs, set up program with line of sight metric, develop a strategy and closely work on execution to achieve program milestone. Key program activities include FE and supporting Time to Mature DPM program and Time to Mature Uncorrectable Error program execution for HBM product and improving customer field DPM excellence. Responsibilities and Tasks Provide Strategic Support in Quality Program/Project Management Develop, manage, and/or communicate quality strategy with line of sight metrics and goals to monitor execution health. Lead cross-functional initiatives or enabling projects that support FLT and companywide quality objectives. Develop and drive compliance in global business process related to product quality. Manage the projects to enable the implementation path for new initiatives. Support program expansion for ID1 including 170s DRAM Provide Tactical Support Work with cross-functional team

What you’ll do Be the generalist EE for the scanner system: integration, bring-up, debugging, and making the electrical side of the device reliable and serviceable. Own ultrasound experimentations that feeds the image reconstruction team Design and execute experiment setups for transducer characterization (element sensitivity, bandwidth, cross-talk mapping, beam profile measurements) and ex vivo / phantom clinical testing. Acquire, process, and analyze RF and baseband signals for data quality assessment and benchmarking. Design simple boards and adapters as needed (monitoring, power/safety, interface/conditioning), and take them from prototype through a stable revision. Prototype quickly, then harden what works: wiring/harnessing, grounding, safety interlocks, and reliable integration across subsystems. Own practical test setups and documentation (fixtures, scripts, procedures) that make experiments repeatable and results comparable over time. What we’re looking for Strong hands-on EE background with experience building, debugging, and iterating on real systems in the lab. Solid understanding of signal processing fundamentals — knows what to measure, how to condition and digitize it, and how to evaluate signal quality in the context of an imaging system (SNR, bandwidth, dynamic range, artifacts). Comfortable spanning system integration + occasional design work (schematics/layout reviews or light PCB design) in a fast-moving environment. Ability to work at the boundary between hardware and algorithms: measure reality, communicate constraints, and help close gaps vs simulation. High agency and practicality: able to set up experiments, get trustworthy data, and unblock others on a lean team. Useful experience Analog/mixed-signal, or high-speed data capture experience; strong instincts for instrumentation and noise/debugging. Ultrasound or acoustic sensor handling: hydrophone calibration and field mapping, transducer impedance characterization, element-level sensitivity