Soc Architecture And Design Engineer in United States

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $1.5B Series F , led by Altimeter Capital, Conviction Partners, and Spark Capital. Join us and help build the platform engineers turn to to ship AI products. THE ROLE We are seeking an experienced and proactive Security Engineer to help us build, maintain, and continuously improve the security posture of our rapidly growing ML infrastructure platform. As one of the first dedicated security hires at Baseten, you will work cross-functionally with engineering and operations teams to ensure we’re meeting the highest standards of confidentiality, integrity, and availability. You’ll have an opportunity to shape our security strategy and best practices from the ground up, influencing the way our platform handles sensitive data for both internal and external stakeholders. RESPONSIBILITIES Security architecture and design: Collaborate with engineering teams to design and implement secure systems and infrastructure, including cloud (AWS/GCP) environments and container orchestration platforms. Vulnerability management: Lead proactive vulnerability assessments, pen tests, and remediation efforts to ensure our products and infrastructure remain secure. Incident response: Develop and maintain incident response processes, including detection, analysis, containment, eradication, and post-incident reviews. Identity and access management (IAM): Oversee IAM strategies and tools to ensure the right people have the right level of access to our systems and data. Security compliance and audits: Work closely with operations to ensure compliance with relevant standards (e.g., SOC 2, ISO 27001) and

Job Details: Job Description: The Role and Impact As a SoC Design Verification Engineer, you will play a pivotal role in ensuring that Intel's complex System-on-Chip (SoC) designs meet functional specifications and deliver high-quality performance. You will design scalable and reusable verification plans, develop test environments, and execute tests to uncover issues and improve functionality. Your contributions will directly enhance Intel's product quality and ensure optimal performance in presilicon development. Business Group You will be joining Intel's cutting-edge product development group, a team focused on designing and verifying advanced semiconductor solutions. This group is at the forefront of innovation, delivering high-quality, scalable products that drive Intel's leadership in technology and performance. By contributing your skills here, you will help shape the future of computing and enable groundbreaking advancements in the industry. Key Responsibilities - Define and develop scalable and reusable block, subsystem, and SoC verification plans. - Create test benches and verification environments that align with microarchitecture specifications. - Execute verification plans, including emulation and system simulation models, to ensure design functionality and uncover bugs. - Debug and root cause issues in presilicon environments, implementing corrective measures to address failures. - Collaborate with architects, RTL developers, postsilicon teams, and physical design teams to improve verification of complex architectural features. - Document and maintain test plans, driving technical reviews with design and architecture teams. - Integrate security coverage activities within test plans, including regression and debug tests. - Maintain and improve

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about driving innovation for next-generation memory solutions powering AI/ML and high-performance computing systems. As a Director of HBM RTL Design and Integration, you will lead a team responsible for the design, integration, and delivery of next-generation HBM SoC logic die, with a strong focus on RTL development and IP integration. You will drive technical strategy and execution across multiple product generations, working closely with architecture, verification, physical design, firmware, and product engineering teams. Key Responsibilities Lead SoC RTL design and integration for HBM logic die, including subsystem partitioning, IP integration, and SoC-level design convergence. Drive translation of architectural and micro-architectural specifications into robust, high-quality RTL implementations across multiple teams. Oversee SoC integration aspects, including clocking, reset, power intent, configuration infrastructure, and system-level design correctness. Establish design methodologies and best practices to improve quality, reuse, and development efficiency across HBM programs. Partner with SoC Architecture, Verification, Physical Design, Firmware, and System teams to ensure successful end-to-end product execution. Work closely with Product Engineering, Test, Probe, Process Integration, Assembly, and Manufacturing to ensure robust, manufacturable HBM

About the job Lead the team that proves our AI silicon performs reliably before it reaches customers. You will build and lead Graphcore's characterisation capability for next generation silicon and system platforms. Your work will help ensure our products perform consistently across real world conditions. You will define bring up and characterisation strategies, lead technical execution, and shape the lab infrastructure needed for success. You'll work across silicon, hardware, manufacturing, architecture and product teams to solve complex engineering challenges. This is a hands on leadership role with the opportunity to influence both product design and how Graphcore validates future AI systems. The team and culture This is a newly formed team within Manufacturing Operations. You'll have the opportunity to establish how the team works while building strong partnerships across engineering and operations. Day to day, you'll work closely with architecture, silicon, hardware, production test and product teams. Decisions are driven by data, technical evidence and close collaboration across disciplines. We value ownership and clear communication. You'll be trusted to lead technical direction, remove blockers and help teams make progress with confidence. What we're looking for Essential Proven track record of delivering complex technical projects as an individual contributor, manager, or project manager, with the ability to work independently and drive execution. Strong expertise in silicon digital device design, bring-up, characterisation, and silicon process technologies, with an understanding of their impact on transistor- and system-level performance. In-depth knowledge of high-performance processors, system-on-chip (SoC) architectures, and high-speed digital interfaces such as PCIe, Ethernet, and DDR. Experience with measurement automation, data analysis, and scripting/coding to develop automated test and analysis workflows, with familiarity of ATE systems and t

What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end: architecture, schematic capture, layout (high-speed digital, analog/mixed-signal, power), DFM/DFT, fabrication and assembly vendor management, bring-up, and revision control. Write firmware for embedded targets (MCU/SoC): drivers, real-time control loops, safety-relevant logic, bootloaders, and field update paths. Audit and update HDL (FPGA) code for high-throughput data acquisition, timing/synchronization, triggering, and pre-processing of ultrasound and sensor data streams. Define electrical interfaces and data contracts with software, recon/ML and mechanical teams: timing budgets, clocking/sync, signal integrity, connectors/harnessing, and failure modes. Establish electrical engineering rigor: design reviews, schematic/layout review checklists, bring-up procedures, test fixtures, and documentation suitable for a regulated medical device program (DHF, traceability, change control). Mentor and grow the electrical function; select and manage external design partners where leverage is high. What we’re looking for Deep experience designing complex boards from blank page to stable revision, including high-speed digital and analog/mixed-signal domains. Strong schematic and layout skills (Altium/KiCad or equivalent) with real signal integrity, power integrity, grounding, and EMI/EMC instincts. Solid embedded firmware background in C/C++ (and Python for tooling): peripherals, DMA, interrupts, real-time constraints, and debugging on hardware. Practical HDL experience (VHDL/Verilog/SystemVerilog) for data acquisition, timing, and streaming interfaces. Track record of owning bring-up and debug on real hardware: scopes, logic analyzers, and disciplined root-cause analysis. Technical leadership: clear trade-offs, strong written documentation, and the ability to set

NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will help to build the high-performance processor elements that implement programmable compute and graphics functionality. What you'll be doing: As a key member of our ASIC Verification team, you will verify the design and implementation of the industry's leading GPUs You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced verification methodologies such as UVM Understand the design and implementation of your unit, define the verification scope, develop the verification infrastructure and verify the correctness of the design Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks What we need to see: Bachelors Degree in EE, CS or CE or equivalent experience 2+ years of relevant experience Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Verdi, GDB) Experience crafting test bench environments for unit and system level verification Strong background in System Verilog or similar HVL Expertise with C/C++ programmin

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are seeking an experienced SoC Architect to lead the definition and development of next-generation custom AI silicon for edge deployments. This role will be responsible for shaping the architecture of highly efficient, high-performance SoCs optimized for machine learning inference and on-device intelligence. You will work cross-functionally with internal engineering teams and external ecosystem partners to translate product requirements into scalable silicon solutions, driving execution from concept through delivery. In this role you will: Define the architecture and technical roadmap for custom SoCs targeted for edge applications. Drive system-level tradeoff analysis across compute, memory, interconnect, power, thermal, and cost constraints. Architect energy-efficient ML compute subsystems optimized for inference workloads and real-world deployment environments. Collaborate with internal hardware, software, systems, and product teams to align architecture with platform needs. Partner with external silicon vendors, IP providers, and manufacturing partners to execute development plans. Lead hardware/software co-design efforts to maximize performance per watt and end-to-end system efficiency. Guide implementation teams through microarchitecture, RTL development, validation, and bring-up phases. Operate effectively in agile development environments and help teams deliver against aggressive schedules and milestones. You might thrive in this role if: Proven exper

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10+, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We're looking for an Engineering Program Manager — or a technical engineer ready to move into program management — to help drive execution on our RISC-V CPU team. You'll work across architecture, design, verification, physical design, and DFT to keep a high-performance CPU program moving from spec through tapeout and post-silicon debug. Partnering with a senior program lead and engineering managers, you'll own schedules, track milestones, surface risks early, and keep cross-functional teams aligned. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experience in CPU, SoC, or silicon development — as an engineer, technical lead, or program manager. Comfortable working with cross-functional engineering teams and translating technical detail into clear status, dependencies, and trade-offs. Organized and proactive; you chase down open items rather than waiting for them to resolve. A clear communicator who can hold your own in engineering discussions and write updates leadership can act on. What We Need Support the full CPU development cycle — spec, design, verification, DFT, ta

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology—and amazing people. We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation products to the market. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers an unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: Drive product performance and power targets, trade-off features/configurations and provide innovative solutions to complex silicon and system level problems. Evaluate new market segments and use cases; translate market requirements to engineering problem statements and metrics. Innovate Performance, power, yield and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter and DL/AI. Develop methodologies and requirements for multi-functional teams to drive silicon and system product features to production. Incorporate productization feedback to improve the next generation. Lead the team for feature requirements and schedule from architecture to silicon phase of projects. Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, HW/S

At Vanta, our mission is to help businesses earn and prove trust. We believe that security should be monitored and verified continuously, and we empower companies to practice better security and prove it with ease. Vanta has a kind and talented team, and while some have prior security experience, many have been successful at Vanta without it. As a Staff Software Engineer on the Automation - Foundations team, you will lead the re-platforming of the data layer underneath Vanta’s entire compliance product. This is a migration that spans multiple teams, has to preserve every public API contract along the way, and cannot lose a single customer’s evidence while it happens. Foundations is Vanta’s data platform team. We ingest security and compliance data from across our customer’s environments, currently tens of thousands of resources per second, with single-customer bursts running into the millions. We store the data, catalog it, make it queryable, and turn it into evidence that has to survive a real SOC 2 or FedRAMP audit. We are in the middle of moving our platform from a Mongo-centric architecture to a schema-aware, Postgres-backed architecture, on a Kafka and S3 pipeline that decouples data fetching from processing. Both pipelines run in parallel today, the hard problems here are correctness under migration, eventual consistency, and multi-tenancy, in a domain where “mostly right” is not an acceptable failure mode. Visit our Vanta Engineering Blog to learn more about what our team is working on. What you'll do as a Staff Software Engineer at Vanta: Lead the migration of Vanta’s resource data model from a Mongo-centric solution to a schema-aware Postgres-backed solution and running both generations in parallel without breaking a customer integration. Drive solutions across teams that you do not own but are dependent on the platform built by your team. Design for correctness under eventual consistency with idempotent session handling, conditional writes that survive out