Soc Static Timing Analysis Engineer Jobs

About the Team DoorDash is one of the world’s leading on-demand logistics platforms. Across DoorDash, Deliveroo, and Wolt, our operations span more than 40 countries, dozens of offices, and tens of thousands of employees.Global Safety and Security helps protect our people, property, operations, brand, and reputation across that footprint, using technology, agility, and a people-first approach to stay ahead of evolving risks. Within the team, Protective Services focuses on the safety of our executives, their families, and the operations that support them. Our detection engineering function brings together enterprise, marketplace, open-source, and physical security signals to identify threats that don’t fit neatly within a traditional SOC boundary. This role builds the detection capabilities that turn those signals into timely, actionable intelligence - and helps Protective Services find what matters before it becomes something bigger. About the Role Detection engineering looks a little different here. As a Detection Engineer on Protective Services, you’ll build the technical capabilities that help identify and investigate threats to protected individuals. The signals you’re looking for won’t live neatly in one place—they may surface across identities and endpoints, cloud environments, marketplace activity, support interactions, physical access events, or open-source information. You’ll connect those signals to find what matters. That means building detections, enrichment, and automation; separating meaningful risk from noise; and investigating what you uncover alongside Protective Services partners. This is a hands-on engineering role where you’ll work across code, queries, data pipelines, detection repositories, and production systems. You’ll take detections from an initial hypothesis through deployment and tuning, then use what happens in the real world to make them better. You’ll have ownership of well-understood problems while partnering with senior engineers whe

WPP is the trusted growth partner for the world’s leading brands. We unite cutting-edge media intelligence and data solutions, world-class creativity, next-generation production, transformative enterprise solutions and expert strategic counsel in a single company – powered by exceptional talent and our agentic marketing platform, WPP Open, to help our clients navigate change, capture opportunity and deliver transformational growth. We work with the world's most valuable brands and have global reach across 100+ markets, with deep local expertise. Our people are the key to our success. We're committed to fostering a culture of creativity, belonging and continuous learning, attracting and developing the brightest talent, and providing exciting career opportunities that help our people grow. For more information, visit WPP.com. Why we're hiring: Detection Engineering is responsible for designing, developing, and maintaining high-fidelity detection logic across enterprise security platforms. This role focuses on proactive threat detection, automation-first practices, and continuous improvement of detection coverage and accuracy, supporting the WPP SOC transformation into an Autonomic Security Operations model. What you'll be doing: Develop, test, and maintain detection rules and logic across SIEM, EDR, NDR, and cloud-native platforms. Regularly review and enhance detection logic to improve accuracy, reduce noise, and align with evolving threats. Work with wider WPP engineering teams to ensure high-quality, normalized telemetry for effective detection. Automate detection rule deployment, QA, and version control using scripting and CI/CD pipelines. Root Cause Analysis (RCA) Conduct RCA on missed detections, delayed responses, and high-severity incidents. Identify technical and process-level causes of detection failures or inefficiencies. Drive corrective actions based on RCA outcomes (e.g., rule improvements,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Security Firmware Engineer on Micron's enterprise SSD team, you will design and develop security features that protect next-generation storage products against evolving cybersecurity threats. You will architect and implement cryptography-based solutions — including data encryption, Root of Trust, Secure Boot, Device Attestation, and Self-Encrypting Devices (SED) — while leading the transition to post-quantum cryptography for future product generations. This role spans the full Security Development Lifecycle, from threat modeling and architecture through implementation, testing, and certification. You will work across SoC, FPGA, and simulation platforms and collaborate cross-functionally to deliver security solutions aligned with industry standards including OCP, TCG, NVMe, and PCIe. Responsibilities Design and develop security features for Micron enterprise SSDs, protecting against cybersecurity threats across the product lifecycle Architect, implement, and debug cryptography-based security solutions including data encryption, Root of Trust, Secure Boot and Update, Device Attestation, and Self-Encrypting Devices (SED) Lead the transition to post-quantum cryptography algorithms (LMS, ML-DSA, ML-KEM) for next-generation products Implement security protocols aligned with OCP, TCG, NVMe, and PCIe specifications Debug security firmware on SoC, FPGA, and simulation platforms using tools such as JTAG, memory dumps, and bus analyzers Dri

Sr. GRC Engineer The Team + The Role Pendo's Information Security team protects the data entrusted to Pendo and helps ensure our products are built with security and privacy by design. The team spans Security Operations, Product Security, and Compliance and Risk. With a small team and broad scope, the work directly supports the security, resilience, and trust of Pendo's products and operations. The Sr. GRC Engineer is an AI-first technical leader who helps drive the evolution of Pendo's governance, risk, and compliance program. This role independently leads complex compliance, risk, and incident-response work while identifying program maturity gaps, translating security risk into business terms, and contributing to security roadmap and investment decisions. Success means building durable controls and programs that reduce risk and operational friction, not simply completing audits. This role is based in our Raleigh office. What this looks like day-to-day AI-driven compliance and operations acceleration: Use AI to accelerate audit evidence preparation, policy documentation, control testing workflows, and regulatory research. Evaluate GRC platform automation capabilities and integrate AI tooling where it reduces manual overhead, then document and share effective approaches with the team. Security program strategy and roadmap: Identify maturity gaps across compliance and security operations and translate them into prioritized roadmap recommendations grounded in business risk. Contribute to security investment discussions, clarify tradeoffs between coverage, cost, and risk, and anticipate emerging regulatory requirements before they become audit findings. Compliance program ownership: Own one or more regulatory compliance programs end-to-end, including SOC 2 Type II, ISO 27001/42001, PCI-DSS, GovRAMP, or FedRAMP. Lead control design, evidence collection, auditor relationships, and remediation tracking to maintain effective and durable compliance programs. Risk assessment

Job Details: Job Description: Join Intel's Silicon and Platform Engineering Group (SPE) as an Exempt Tech Contract Employee, The Role and Impact :As a Power Integrity Engineer, you will play a pivotal role in ensuring Intel's platforms and products meet the highest standards of performance and reliability. This position offers you the opportunity to work on cutting-edge technologies, designing and optimizing power delivery networks for complex high-speed platforms, boards, packages, and silicon. Your contributions will directly impact Intel's ability to deliver industry-leading solutions to its customers, driving innovation in power integrity and enhancing the performance and functionality of our silicon and systems. Join us to tackle exciting challenges and create impactful solutions that push technological boundaries. The primary responsibilities for this role will include, but are not limited to: Develop and analyze power delivery networks, including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards. Define power grid specifications and power and area targets to achieve optimal balance between power integrity and performance. Design test structures, electrical analysis methodologies, and verification plans to address power integrity challenges. Perform measurements to characterize power noise profiles across frequency, ground bounce, and other critical metrics, verifying power delivery networks post-design. Correlate measurements back to presilicon analysis and estimations for improved accuracy. Apply expertise in power integrity design and tradeoffs to guide simulations of power networks and physical implementations for packages and platforms. Ensure on-die power noise meets system-on-chip (SoC) functionality an

As one of the technology industry's most desirable employers, NVIDIA has been redefining accelerated computing, computer graphics and leading the Artificial Intelligence revolution. NVIDIA's innovation is fueled by its great technology—and amazing people. We are seeking a Senior Silicon and System Product Lead to influence, innovate and take our next generation products to the market. As part of the Silicon Solutions Team, we architect and deliver groundbreaking system solutions that integrate all aspects of the system from silicon design, software design to operations and final deployment in multiple market segments that NVIDIA serves. This position offers an unique opportunity to collaborate with multiple organizations in the company and grow your career in a high impact role. We need a passionate, hard-working and creative individual to lead the products all the way from market analysis to delivering the features on the final product. What you'll be doing: Drive product performance and power targets, trade-off features/configurations and provide innovative solutions to complex silicon and system level problems. Evaluate new market segments and use cases; translate market requirements to engineering problem statements and metrics. Innovate Performance, power, yield and quality optimizations and features for the world’s fastest power-shipping products in the GPU and SoC market segments spanning gaming, automotive, datacenter and DL/AI. Develop methodologies and requirements for multi-functional teams to drive silicon and system product features to production. Incorporate productization feedback to improve the next generation. Lead the team for feature requirements and schedule from architecture to silicon phase of projects. Work alongside system architects, designers, marketing teams, chip and board designers, software/firmware engineers, HW/S

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. This Notice is provided as a result of the filing of applications for permanent alien labor certification for the positions noted below. Any person may provide documentary evidence bearing on an application to the Certifying Officer, U.S. Department of Labor, Employment and Training Administration, Office of Foreign Labor Certification, 200 Constitution Avenue NW, Room N–5311, Washington, DC 20210. Employer: Micron Technology, Inc. Job Title: Firmware Engineer Job Requisition: JR42883 Job Location: Longmont, Colorado Job Type: Full Time Rate of Pay: $100,000 to $254,000 Duties: Develop high-performance controller firmware for innovative volatile and non-volatile memory systems. Assist in evaluating, designing, building, bench testing, debugging, and failure analyzing firmware for new high-performance memory controllers and Solid State Drives that will increase performance, while reducing power, latency and SoC (System on Chip) complexity for the target markets. Work closely with system test engineers, system failure analysis engineers, firmware engineers, firmware test engineers, system hardware design engineers, product engineers, memory design engineers, firmware tools developers, and production engineers to solve cross-functional product development issues. Validate customer requirements and perform failure analysis on FW related issues. Develop structure

Job Details: Job Description: Do Something Wonderful At Intel, we put silicon at the center of the world’s most meaningful innovations. From personal computing and AI to cloud-scale data centers and edge platforms, our processors power technologies that touch billions of lives. If you’re passionate about building world-class silicon at massive scale, we want to build the future with you. The Team You’ll join Intel’s All Cores Engineering (ACE) organization, the team responsible for designing and delivering Intel’s industry‑leading CPU cores. Within ACE, the Atom group focuses on high‑efficiency, performance‑per‑watt optimized cores that enable everything from client platforms to emerging edge and scalable solutions. This is a hands‑on senior engineering role with direct impact on next‑generation CPU silicon. What You’ll Do As a Senior CPU Design Verification Engineer you will play a critical role in ensuring architectural correctness, functional robustness, and power‑efficient performance of Intel’s Atom CPU designs before first silicon. Key responsibilities include but not limited to the following: Lead pre‑silicon functional verification of complex CPU and SoC logic to ensure full compliance with architectural and microarchitectural specifications. Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments, ensuring comprehensive functional and coverage closure. Define, run, and analyze system‑level simulations to uncover functional, performance, power, and corner‑case issues. Debug and root‑cause complex RTL, microarchitecture, and integration issues; drive issues to resolution with design teams. Collaborate cross‑functionally with CPU architects, RTL de

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity We are seeking a system validation engineering intern to help drive server blade and rack validation efforts for next-generation AI infrastructure hardware systems. This role focuses on post-silicon system validation across the full lifecycle of server hardware systems, ensuring functional and performance meets product objectives. You will help drive end-to-end blade and rack validation including development, execution, and debug while collaborating across silicon, firmware, systems, and platform teams. The Blade and Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Help drive and execute post-silicon validation goals of AI compute blades and racks including testcase planning, development, and automation Help drive validation testcase execution and system debug against program achievements and report validation progress and risks. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness Triage test failures, collect debug data, and collaborate on root cause analysis. Track validation coverage and continuously improve test processes and infrastructure. What You’ll Bring Working towards a Bachelor's

At Beyond Finance, we've made it our mission to help everyday Americans escape the endless cycle of crippling debt and step into a brighter financial future. Through compassionate, individualized care, a culture focused on compliance and ethics, supportive user-centric technology, and customized financial solutions, we've helped over 1 million clients on their path to a brighter future. While we're proud of what we've already accomplished, we're searching for new collaborators to help us get to the next level! If you're looking to join a forward-thinking, rapidly growing organization with helping people as its number one goal, we want to hear from you. The Role You'll build the detections and automation that protect our cloud, SaaS applications, and user workstations. You'll be the team's Datadog expert, owning how security telemetry gets into Datadog Cloud SIEM, how it's filtered, and the detections that run on it. You'll also automate the repetitive work around alerts and support triage and investigations. As we bring automation and AI into security operations, you'll help build and ship the new capabilities. What You'll Own Detection engineering: write, tune, and retire Cloud SIEM detections, and map coverage to MITRE ATT&CK to close gaps. Logging pipeline: onboard sources and build Datadog log pipelines that parse, normalize, and enrich security telemetry. Detection-as-code: manage detections in version control with testing and peer review. Automation: build workflows for alert enrichment, triage, containment, and notification. AI in the SOC: build AI-assisted triage and alert summarization, with a human in the loop. Measurement: track coverage, false-positive rate, and automation rate to decide what to fix next. Filtering and cost: manage indexes, exclusion filters, and retention tiers to cut noise and cost without losing coverage. Security operations: support triage, investigations, and incident response, including on-call. What You Bring 3+ years in secur

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Join forces with us on our mission to build a better IT industry. We are currently looking for a highly skilled Embedded Software Engineer to our team in Stockholm or Malmö, Sweden. Please note that applicants must live in Sweden and hold a valid work permit at the time of application to be considered for this role. Responsibilities: Design, implement, and debug embedded firmware for 802.15.4 Thread-based devices (border routers, RCPs, sleepy/end devices) running on an RTOS and embedded Linux Integrate and maintain the OpenThread stack and Matter commissioning/data-model layers across the product line Work closely with hardware engineers on SoC/MCU bring-up and debug radio timing, RF, and low-power issues at the driver level Implement and troubleshoot Thread border routing, SRP, and network commissioning/joining flows, including bridging to Wi-Fi/Ethernet backbones Diagnose firmware-level issues using JTAG/SWD debuggers, logic analyzers, and protocol sniffers/packet captures Write and maintain unit and integration tests; participate in code review Contribute to OTA update pipelines and manufacturing/production test tooling Requirements: Strong proficiency in C++ (99 % code base) and C for embedded systems Hands-on experience with an RTOS (FreeRTOS, Zephyr, or similar) Solid MCU debugging skills Solid networking fundamentals, incl

About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you’ll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Join forces with us on our mission to build a better IT industry. We are currently looking for a highly skilled Embedded Software Engineer to our team in Stockholm or Malmö, Sweden. Please note that applicants must live in Sweden and hold a valid work permit at the time of application to be considered for this role. Responsibilities: Design, implement, and debug embedded firmware for 802.15.4 Thread-based devices (border routers, RCPs, sleepy/end devices) running on an RTOS and embedded Linux Integrate and maintain the OpenThread stack and Matter commissioning/data-model layers across the product line Work closely with hardware engineers on SoC/MCU bring-up and debug radio timing, RF, and low-power issues at the driver level Implement and troubleshoot Thread border routing, SRP, and network commissioning/joining flows, including bridging to Wi-Fi/Ethernet backbones Diagnose firmware-level issues using JTAG/SWD debuggers, logic analyzers, and protocol sniffers/packet captures Write and maintain unit and integration tests; participate in code review Contribute to OTA update pipelines and manufacturing/production test tooling Requirements: Strong proficiency in C++ (99 % code base) and C for embedded systems Hands-on experience with an RTOS (FreeRTOS, Zephyr, or similar) Solid MCU debugging skills Solid networking fundamentals, incl

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. System Integration sits at the intersection of all of them. It is the layer where every architecture, design, software, and manufacturing decision meets reality. When something breaks late in a program, it usually breaks here first. We are hiring a Senior Manager to lead this team in the US and partner closely with teams globally. Your work will sit on the critical path of every NVIDIA silicon program, and the bar you set for system integration is the bar we ship to! The two hardest, highest-leverage problems in this seat: Find critical silicon issues earlier — often before software is production-ready. Left-shifting post-silicon coverage is the highest-value thing System Integration can do. Standing up wide-area testing as a repeatable capability is a core part of the role. Keep programs on milestone when upstream dependencies slip. Validation plans collide with reality every program! The team needs new strategies, not just contingency plans, to keep moving when software, firmware, or methodology slip. You will design and run those strategies. What you’ll be doing: Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs. Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready. Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation. Deve

At Qualia, we've built the leading B2B real estate technology that transforms the home buying and selling experience into a simple, secure, and enjoyable process. Our SMB and Enterprise products bring together users from across the real estate ecosystem—homebuyers and sellers, lenders, title and escrow agents, and real estate agents—onto a single shared digital closing platform, providing greater clarity and transparency to real estate transactions. Today, through our business customers across the country, millions of consumers use Qualia to close on homes every year. WHAT YOU'LL WORK ON Qualia's platform sits at the center of the money movement and recordkeeping that closes a real estate transaction. Our customers, their regulators, underwriters, and auditors need durable assurance that the controls behind that platform work. Building and running that assurance function is the job. As Senior Manager, Internal Controls, you will own Qualia’s SOC 1 program end to end, from readiness through a recurring examination, and run the internal audit and control testing that supports our SOC 2 program. Today much of our SOC readiness work is supported by outside consultants; a core goal of this role is to bring that capability in-house and become the internal owner of it. Over time, the mandate expands: as Qualia scales, this role grows into the foundation of a broader internal audit function covering financial, operational, and compliance risk across the company. This is a high-visibility individual contributor role reporting to the VP of Finance, with regular exposure to the executive team, external auditors, and customer teams. RESPONSIBILITIES Own the SOC 1 program end to end: Drive Qualia’s SOC 1 readiness and examination lifecycle including control design, process narratives, risk and control matrices, evidence collection, gap remediation, and management of the external audit across our suite of products. Run internal audit for SOC 2: Plan and execute intern

Job Description About Us OpenFX is on a mission to move money as freely as data, unrestricted by time zones, banking hours, or legacy systems. We are building the infrastructure that will power the next generation of cross-border payment systems for institutions. The team's execution has been exceptional, and we're scaling at a remarkable pace. Our stellar early team comes with experience in companies like J.P. Morgan, Goldman Sachs, FalconX, PayPal, Affirm, Polygon, Kraken, Nium & others. We're backed by Accel, Lightspeed, NfX and other top-tier investors. Role Overview OpenFX processes billions of dollars in transaction volume every month across global corridors. DevOps owns the infrastructure every product runs on, from the cloud foundations through to the delivery path and the recovery posture, for our trading, banking, payments and settlement products. Key Responsibilities Lead and support a DevOps pod of 10+ engineers. You are accountable for the roadmap, the engineering standards and the cloud budget. You create the conditions in which the team can deliver them. Own the resilience of our systems. Design the failover and prove it with regular drills. Own compliant infrastructure: build the controls for DORA, PCI DSS, SOC 2, ISO 27001 and GDPR into the platform itself (IaC policy, least-privilege and just-in-time access, change management, audit logging, data residency). Own the delivery path: CI/CD, environments, artefact and secrets management, progressive rollout and rollback. Our peers should be able to ship when they need to, without filing a ticket. Own observability and support incident response: SLOs for tier-1 services, alerting, fast DevOps escalation support for the on-call team, and blameless post-mortems. Stay close to the work. You know the systems well enough to review a design, help debug an incident and roll up your sleeves when the team needs an extra pair of hands. Lead in service of the team. Clear the path so engineers can do their best