Soc Static Timing Analysis Engineer Jobs

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The Architecture team at Tenstorrent is designing the central compute chiplet that powers our next generation automotive SoC. This role is about turning real world automotive and safety requirements into architecture that performs, scales, and ships fast and reliably. If you think silicon design should start with clarity and end with confidence, this is where your experience makes the biggest impact. This role is remote, based in Munich, Germany. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Approach design with a systems mindset, always thinking in trade offs, not just specs and block diagrams. Bring deep knowledge of SoC architecture, from interconnects and I/O to memory and CPUs. Confident working within performance, power, and reliability constraints. Familiar with, or eager to dive into, functional safety, ISO 26262, and automotive grade design challenges. What We Need Someone to architect and specify one or more chiplets in the robotics and automotive family. 5+ years of experience translating high level requirements into detailed architectural direction. Ability to identify impactful features that boost PPA, safety, and reliab

As a SOC Engineer / Detection Engineer, you will be responsible for detecting, investigating, and responding to security incidents across our environment, while continuously improving how we detect and handle threats. You will work hands-on with our SIEM and incident response processes, and act as a key point of contact between the SOC and other engineering/security teams. Depending on your profile, some of your responsibilities can include: - Incident Response: Lead and support the end-to-end response to security incidents, from detection through containment, eradication, and recovery. - Security Investigation: Conduct in-depth investigations into suspicious activity and alerts, correlating data across logs, endpoints, network, and cloud sources to determine root cause and impact. - Post-Mortems & RCAs: Drive post-incident reviews and root cause analyses (RCAs), documenting timelines, findings, and actionable follow-ups. - SIEM Engineering: Implement, tune, and maintain SIEM use cases, detection rules, correlation logic, and alerting to reduce false positives and close detection gaps. - SIEM Support: Provide ongoing support for the SIEM platform, including onboarding new log sources, troubleshooting data ingestion, and maintaining dashboards/reports. - Cross-Team Collaboration: Partner with Engineering, IT, and other Security teams to remediate findings, validate fixes, and share threat context. - Process Improvement: Identify gaps in detection, response, and documentation, and drive improvements to playbooks, runbooks, and SOC workflows. **Must have:** - Incident Response: Hands-on experience handling security incidents, including triage, containment, and coordination across teams. - Investigation Skills: Strong analytical ability to investigate alerts and logs (SIEM, EDR, network, cloud) and determine root cause.

Zscaler (NASDAQ: ZS) accelerates digital transformation so customers can be more agile, efficient, resilient, and secure. The Zscaler Zero Trust Exchange™️ platform protects thousands of customers from cyberattacks and data loss by securely connecting users, devices, and applications in any location. Distributed across 160+ public exchanges globally and thousands of private exchanges at the edge, the SASE-based Zero Trust Exchange is the world’s largest in-line cloud security platform. We believe the future of work is Human + AI and are building an AI-native enterprise where human potential is amplified by machine intelligence to solve the world’s hardest security challenges. Driven by deep customer obsession, we are committed to the mission, outcome, and to each other. We bring these commitments to life through three core behaviors: ownership and collaboration, trust through outcomes and impact, and a challenge culture with ongoing feedback. Ready to make an impact at the company pioneering security transformation in the AI era? Join us at Zscaler. Role We are looking for a Senior SOC Analyst to join our team . This is a remote role, reporting to the Global SOC Manager in the Enterprise Security department . As a key guardian of our infrastructure, you will monitor, detect, and analyze security incidents to protect our digital assets . You will be the first line of defense, ensuring that potential threats are mitigated promptly and effectively to maintain a secure environment . What you’ll do (Role Expectations) Monitor security alerts and events to identify potential threats and vulnerabilities Detect and analyze security incidents using multiple security tools Respond to security incidents promptly, following established procedures and protocols Conduct in-depth analysis of security events to determine the scope and impact of potential threats Perform phishing incident analysis Who You Are (Success Profile) You thrive in ambiguity. You're comfortable building the

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering, Computer Engin

Job Details: Job Description: The Role and Impact Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of complex SoC (System-on-Chip) designs. You will work closely with cross-functional teams, influencing designs from concept to production, and ensuring our products meet the highest quality standards. In this role, you will develop innovative DFT/DFD methodologies, optimize workflow with AI, and enhance post silicon efficiency. Your work will directly impact Intel's ability to deliver world-class semiconductor solutions that advance technology across industries. Key Responsibilities : Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency. Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements. Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements. Collaborate with post-silicon teams to debug and validate DFT features. Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows. Qualifications: Minimum Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in DFT, SoC design, or related semiconductor design areas. Expertise in RTL design using hardware description languages like Verilog, VHDL, or SystemVerilog. Preferred Qualifications : Familiar with AI application. Familiarity w

Skeletons, lasers, tattoo buses — the Torq brand grabs attention like nothing else in cybersecurity. And we're growing like crazy, backed by Series D funding, 200% employee growth, and 300% revenue growth. Fueling Torq's momentum is our game-changing AI SOC platform, backed by a team and culture that makes Torq one of Forbes' Best Startup Employers in America, and a Business Insider 'startup to bet your career on'. Life at Torq is all gas, no brakes. We're a team of relentless, collaborative go-getters pushing the boundaries of what's possible for security automation. Every role is an essential driver of Torq's success as the AI-native autonomous SecOps platform of choice for security teams across the Fortune 500. About Torq Torq is the AI SOC platform transforming how enterprises run security operations. By combining a battle-tested hyperautomation engine with agentic AI, Torq lets security teams triage, investigate, and respond to threats at machine speed — moving beyond the limits of legacy SOAR and SIEM. Torq's AI agents act as digital analysts that work 24/7 to triage alerts, investigate threats, and remediate autonomously, freeing human analysts to focus on higher-value strategic work. Torq is defining and leading the AI SOC category, and the market recognition backs it up: Unicorn — closed a $140M Series D at a $1.2 billion valuation in January 2026, bringing total funding to $332M . Gartner — named the "Company to Beat" in AI SOC Agents for Threat Investigation (May 2026). KuppingerCole — named a Leader across all four AI SOC categories : Overall, Product, Innovation, and Market (April 2026). 4.8/5 rating on Gartner Peer Insights. ~300% revenue growth in 2025 , with a global team scaling fast. There's electricity in the air at Torq. We're a dynamic, highly motivated team propelling our customers and partners to new heights through AI-driven security operations. This Professional Services role sits at the front of the fastest-moving category in cybersec

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. You will join an inclusive, forward-thinking team dedicated to building technologies that power virtual reality, neural networks, and next‑generation computing. In this role, you will own design for test (DFT) solutions for complex high‑bandwidth memory (HBM) system‑on‑chip (SoC) base‑die designs. Your work will directly enable manufacturability, quality, and successful silicon bring‑up across current and future HBM generations. (LLM) Responsibilities will include, but are not limited to: Own SoC-level DFT structures and their implementation. This includes scan, memory built-in self-test (MBIST), logic built-in self-test (LBIST) where applicable, boundary scan (JTAG), and test access architectures for HBM base-die builds. Define and drive DFT architecture early in the design cycle, ensuring alignment with SoC integration, floorplanning, timing, power, and physical design requirements. Implement and integrate DFT logic at block, s

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next‑generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high‑performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Design and implement RTL for SoC‑level blocks and subsystems used in HBM logic die. Integrate internal and third‑party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY‑adjacent logic). Collaborate with SoC architects to translate architectural and micro‑architectural specifications into high‑quality RTL implementations. Participate in SoC‑level integration activities, including clocking, reset, power intent, and configuration infrastructure. Assist with pre‑silicon validation and post‑silicon bring‑up, including root‑cause analysis of silicon issues. Contribute to design documentation, block specifications, and design reviews. Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds. Minimum Qualifications Bachelor’s or master’s degree in electrical engineering,

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. The Role We are seeking a thorough SOC Physical Verification & Integration Specialist to drive the physical assembly and signoff of our next-generation SOCs. In this role, you will own the physical integration strategy from the floorplan stage through to tapeout, ensuring seamless assembly of massive multi-hierarchical blocks. You will act as the critical bridge between block-level implementation, top-level integration, and final foundry signoff, ensuring that complex physical bottlenecks are resolved without compromising power, performance, or area (PPA). Key Responsibilities Top-Level Physical Integration: Drive the full-chip physical assembly of very large-scale SOCs (e.g., multi-billion transistor designs). Manage top-level floorplanning, bump planning, global power grid (PG) integration, and top-level clock/routing integration. Hierarchical Verification Methodology: Architect and deploy highly efficient, hierarchical physical verification (PV) flows. Define the boundary conditions, abstraction models, and interface rules required to assemble heavily partitioned, massive-scale designs. Signoff Execution & Debugging: Own full-chip DRC, LVS, ERC, Antenna, ESD, and Latch-up signoff using industry-standard tools (e.g., Siemens Calibre) at advanced process nodes (5nm, 3nm, or below). Cross-Functional Collaboration: Partner tightly with the Physical Design (PD

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

About Graphcore At Graphcore, we’re building the future of AI compute.We’re a team of semiconductor, software and AI experts, with deep experience in creating the complete AI compute stack - from silicon and software to infrastructure at datacenter scale.As part of the SoftBank Group, backed by significant long-term investment, we are delivering key technology into the fast-growing SoftBank AI ecosystem.To meet the vast and exciting AI opportunity, Graphcore is expanding its teams around the world.We are bringing together the brightest minds to solve the toughest problems, in a place where everyone has the opportunity to make an impact on the company, our products and the future of artificial intelligence. Job Summary Our team is at the forefront of the artificial intelligence revolution, enabling innovators from all industries and sectors to expand human potential with technology. The availability of specialised artificial intelligence compute will be a decisive factor in AI’s rate of progress. Graphcore allows innovators to go further, faster. What we do really makes a difference. Reporting to the Director of Silicon Architecture, the SoC Architects are responsible for the design, specification, modelling and integration of sub-systems within complex, high performance and highly integrated silicon devices at the forefront of AI acceleration technology. The role involves close collaboration with other groups, including architecture, silicon design, verification, hardware and software teams. The Team The Silicon Architecture Team sits within the COO group. The SoC architects are responsible for the architectural specification, integration, modelling, validation and evaluation of numerous critical&nb

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we’re building cutting-edge hardware and software solutions that power AI, HPC, and general-purpose workloads. As a Performance Architect on our Platform Architecture team, you’ll work across ML software stacks, compilers, CPU design, cache coherency protocols, and interconnect fabrics to shape the future of high-performance systems. This role is all about bridging software execution and silicon design—making data-driven decisions that directly influence our SoC performance. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Passionate about solving complex system-level performance problems. Comfortable working across hardware and software boundaries. Analytical and data-driven, with a talent for turning workloads into architectural insights. Collaborative, thriving in cross-functional teams spanning compilers, CPU, and interconnect. Excited to shape the future of AI/HPC platforms through performance architecture. What We Need BS/MS/PhD in EE, ECE, CE, or CS Deep understanding of NoC topologies, routing algorithms, QoS, and traffic scheduling. Expertise in cache coherenc

Junior SOC 2 Type 2 Auditor Position Overview Clearwater is looking for a Junior SOC 2 Type 2 Auditor to support the planning, execution, and documentation of SOC 2 Type 2 audits. The role will work closely with internal teams, control owners, external auditors, and compliance stakeholders to assess the design and operating effectiveness of controls and ensure appropriate audit evidence is maintained. The ideal candidate should have good understanding of SOC 2, IT general controls, information security, risk management, and compliance frameworks , with strong attention to detail and documentation skills. Key Responsibilities Support SOC 2 Type 2 audit activities from planning through completion. Assist in reviewing and testing controls related to security, availability, confidentiality, processing integrity, and privacy, as applicable. Collect, organize, and validate audit evidence from control owners. Perform preliminary testing of controls for design and operating effectiveness under the supervision of senior auditors. Review evidence for completeness, accuracy, relevance, and appropriate audit periods. Identify control gaps, exceptions, and missing evidence and communicate them to relevant stakeholders. Maintain audit workpapers, testing documentation, evidence trackers, and issue logs. Follow up with control owners to obtain missing or updated evidence. Assist in preparing audit findings and documenting observations, exceptions, and remediation activities. Support management in tracking remediation plans and closure of identified control deficiencies. Participate in walkthroughs and discussions with IT, Security, Engineering, HR, Legal, Finance, and other business teams. Assist with maintaining SOC 2 policies, procedures, control descriptions, and supporting documentation. Stay current with SOC 2 requirements, security and compliance practices, and relevant industry standards. Required Qualifications Bachelor's degree in Infor