Soc Static Timing Analysis Engineer Jobs

NOC / SOC Technician (2nd Shift) — Hampton, Vatican City State (Holy See). Apply via Workday.

Senior SoC Chiplet Architect — 6 Locations. Apply via Workday.

Custom SOC IP Verification Engineer — 2 Locations. Apply via Workday.

The Role We are seeking a highly skilled and hands-on SoC Floorplan Lead to own the physical foundation of our next-generation AI and Data Center SoCs. In this critical role, you will be the bridge between architecture, logic design, and physical design. You will work hand-in-hand with Chip Architects and RTL Leads to influence micro-architecture and ensure the physical implementation achieves best-in-class Power, Performance, and Area (PPA). If you love solving complex spatial puzzles on advanced technology nodes, integrating sensitive analog components, and driving execution in a high-energy start-up environment, this is the role for you. Key Responsibilities Top-Level Floorplanning: Own the SoC-level floorplan from concept to tape-out for high-performance, large-scale AI/Data Center chips on advanced process nodes (e.g., 5nm, 3nm or below). Architecture & RTL Collaboration: Partner closely with Architecture and RTL teams to provide early physical feasibility feedback. Drive block partitioning, shape optimization, and data-flow planning to achieve the absolute best PPA. Bump & Package Co-Design: Lead bump planning and IO ring definition. Work with packaging teams on flip-chip/advanced packaging constraints, ensuring optimal signal escape and power delivery. Custom & Analog Routing: Manage the placement and custom routing strategies for critical Analog/Mixed-Signal (AMS) IPs, high-speed SerDes (PCIe, Ethernet, Memory interfaces), PLLs, and sensitive clock distributions. Power Delivery Network (PDN): Design and analyze the top-level power grid, ensuring robust power delivery for high-current AI workloads while minimizing IR drop. Pin Assignment & Feedthroughs: Manage macro placement, block-level pin assignments, and top-level feedthrough planning to optimize global timing and routing congestion. Methodology Development: Build and maintain scalable Floorplanning workflows and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job responsibilities: · Create SoC Verification plan and develop C/SV/UVM based SoC verification tests · Develop understanding on SoC Architecture and Test controller Architecture · Develop SV / UVM based testcases for Test controller verification, MBIST verification and Functional vectors generation · Develop SV/UVM monitors to measure performance and improve Verification Environment · Interact with Architecture/Design/Tester teams to identify ASIC test vectors and functional patterns requirement · Develop flows to automate verification environment development and drive team · Involve in Vectors Bring-up activity and support ATE/Tester teams for Functional Characterization Job Qualifications · Bachelors/Masters in Engineering. · Minimum 7&#43; years of SOC/IP Verification based on SV/UVM. Proficient in using AI tools and Methodologies · Good understanding on Test controller / MBIST / DFT architecture · Knowledge of industry standard interfaces, such as PCIE, LPDDR*, ONFI/NAND is desired. · Proven experience in ATE/Functional CHAZ vector enablement in Silicon / Wafers and debug abilities on vectors <p

Staff Design Engineer - SOC — Singapore. Apply via Workday.

Graphcore Senior Principal AI SoC Validation (Bring-up lead) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. We are developing the next generation of AI compute, a large-scale system-on-chip (SoC) designed to power future high-performance AI systems. As the SoC Validation Lead, you will be responsible for enabling pre-production software to run reliably on new silicon quickly and efficiently, before showing that the silicon meets the highest standards of quality, reliability and functionality, ready for production deployment. You will lead a team delivering post-silicon validation across the full AI SoC, working across silicon, firmware, and platform levels. The role requires a deep technical understanding, strong hands-on debug experience, and the ability to collaborate effectively with hardware, software, and systems engineering teams. Key responsibilities Define and lead post-silicon validation strategy Develop and refine the overall post-silicon validation approach for our AI SoCs, ensuring reliable and timely delivery of validated silicon, architectural correctness, feature robustness, and at-scale system reliability. Drive cross-domain debug and issue resolution Lead investigation and resolution of complex issues spanning silicon, firmware, operating systems, and platform interactions. Ensure that fixes are effective and sustainable. Promote collaboration and shared understanding Work closely with

Principal Engineer – ASIC SoC Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Intern - HBM SoC RTL Design Engineer — Folsom, CA. Apply via Workday.

System Software Engineer – GPU and SOC (2027 RDSS Intern) — Taiwan, Taipei. Apply via Workday.

Staff/Principal Engineer - Design Verification (SoC expert/lead) — San Jose, CA. Apply via Workday.

We are now looking for a Senior Architect for GPUs and SoCs: The NVIDIA Architecture Modelling group is looking for architects and software developers to join our various architecture efforts. A key part of NVIDIA's strength is to innovate in the graphics and parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our GPU architecture and maintain our leadership. In this position, you will be working with other world-class architects on modeling, analysis and validation of chip architectures and features that advance the state of art in performance and efficiency. What you'll be doing: Modeling and analysis of graphics and / or SOC algorithms and features Work in a matrixed environment, across the different modelling teams, to document, design, develop tools to analyze and simulate, validate, and verify models Familiarize with the different models (functional and performance) that are used at Nvidia and help with feature implementation as required. Develop tests, test plans, and testing infrastructure for new architectures/features. Code coverage analysis and reporting Mentor younger engineers and help sustain good coding practices. Learn about newer modelling techniques and frameworks, evaluate the best solution for our needs and work with your manager to drive the change Help develop AI based tools to increase efficiency. What we need to see: Bachelors Degree (or equivalent experience) in a relevant discipline (Computer Science, Electrical Engineering or Computer Engineering) 8&#43; years of relevant work experience or MS with 5&#43; years of experience or PhD with 2&#43; years of experience Strong programming ability: C&#43;&#43;, C along with a good understanding of build systems (CMAKE, make), toolchains (GC

NVIDIA Architecture Modeling group is looking for Architects, Functional Modeling Engineers, and Simulation experts to join various architecture efforts across GPU/ SOC Architecture teams. A key part of NVIDIA's strength is to innovate in parallel computing fields, delivering the highest performance in the world for high-performance computing. We are constantly looking for ways to improve our SoC and Systems architecture and maintain our leadership. In this position, you will be working with other world-class architects on modeling, analysis and validation of chip & system architectures and features that advance the state of art in performance and efficiency. What you'll be doing: Modeling and analysis of SoC & Systems algorithms and features, across datacenter, automotive, and client products Build and deliver platforms for SOC's that enable left shift for the SW teams aligned with project milestones Work closely with the SOC architects and guide modeling teams to deliver high-quality functional models that involve SOC&#43;GPU use cases Collaborate with our EDA partners to align on customer-facing technologies Develop tests, test plans, and testing infrastructure for new architectures/features and code coverage analysis and reporting Ensure alignment between the various modeling teams at NVIDIA, GPU modeling teams, and modeling teams overseas What we need to see: Master’s or PhD in Computer Science, Electrical Engineering, Computer Engineering, or a related relevant field (or equivalent experience) with 5&#43; years of relevant work experience. Strong programming ability: C&#43;&#43;, C along with a good understanding of build systems (CMAKE, make) , toolchains (GCC, MSVC) and libraries (STL, BOOST) Computer Architecture background with experience in modelling wit

What We Do: Cybercrime is growing, and more businesses are getting hit by threats that used to target only the biggest organizations. That pushes defenders like us to operate at the highest level, and it deepens our need for good people who want to make a meaningful impact. Founded in 2015 by former NSA cyber operators, Huntress is a remote-first team working to make enterprise-grade cybersecurity accessible to businesses of all sizes. We work closely with security teams and service providers protecting complex environments, often without the time or headcount to handle it all. That’s why we build our technology in-house and back it with a 24/7 human-led Security Operations Center (SOC). As a result, our platform is never disconnected from the experts who manage it, ensuring our customers' protection. Huntress now secures more than 5M endpoints and 16M identities worldwide. Those numbers keep growing because more businesses rely on us to help carry the load and operate with more confidence. Every day, you can see that commitment in how we stand with our customers and how we show up for each other. Reports To: Director of Product Management, Platform Location: Remote US Compensation: $190,000 to $220,000 base plus bonus and equity About The Role: We are building a product management organization to own and drive our product strategy, and we are looking for an experienced product manager to own a new team focused entirely on Security tooling for the Huntress SOC. Our SOC is the cornerstone of the Huntress Security Platform, serving SMB and mid-market clients through MSP/MSSP and Reseller channels. It delivers premium, human+AI services at a scale most companies can't match — Rapid Response, Tactical Response, and Hypercare together accounted for roughly 150 engagements in a single recent month. Much of that delivery still runs on an internal SOC platform that does not match analysts' current needs - this includes spreadsheets, Slack threads, and per-engagement documen

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Member of Technical Staff, SoC Power and Physical Architect in the Next-generation HBM Architecture Team, you will drive SoC-level specification 3D-stacked, high-performance memories. Apply your knowledge to analyze SoC trade-offs in close collaboration with peer architecture and design teams. Drive power architecture, physical planning, and early SoC design activities, including definition of IP interfaces (e.g., signals, power delivery), clocking, power sequencing, design-for-test, floorplanning, and specification development. Responsibilities: Define clocking architectures, power sequencing, power delivery, and on-die signal interfaces. Define and analyze on-die power delivery networks (PDN) and full-chip thermal implications, including power hot-spot identification and mitigation. Define DFT architectures (e.g., scan chain topology) and set verification requirements. Define SoC floorplans in collaboration with physical designers. Compose and maintain clear SoC physical documentation. Preferred Qualifications: Experie