Sr Design Quality Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry. Join us as a Senior Verification Engineer and contribute to modular, scalable verification solutions for next-generation HBM DRAM products! You will work independently within a multi-functional team of technical domain experts, spanning both IP-level and SoC-level verification. You will collaborate with Design Engineering, Product Engineering, and Business Units to complete the HBM verification roadmap. You will apply your solid understanding of testbench architecture, custom or SoC verification methodologies, and 2.5D & 3D package integration to evaluate issues, define solutions, and broaden your expertise. Responsibilities: Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions Build and improve verification methodology components and GenAI applications aligned to HBM design cycles, broadening cross-disc

Sr Human Factors Design Engineer — 2 Locations. Apply via Workday.

Sr. Design Validation Product Engineer, DEG — Boise, ID - Main Site. Apply via Workday.

Sr. Design Verification Engineer — Minneapolis, MN. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Design/Senior Design Engineer – NAND digital (NVE Engineering) Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. department Introduction The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with cross-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. Position Overview As a Logic Design Engineer in the NVEG organization at Micron Semiconductor Italia, you will play a key role in the definition, implementation, verification, and silicon validation of NAND Flash logic features. In this role, you will act as a technical owner of complex logic functionalities, working at the intersection of architecture, firmware, datapath, analog, and test teams. You will contribute to new product pathfinding, ensure robust feature implementation across technology generations, and support silicon bring‑up, validation, and learning. Responsibilities Responsibilities include, but are not limited to: • Own end-to-end development of logic features, from architecture definition through RTL implementation, verification, and post-silicon validation. • Translate system and firmware requirements into micro-a

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. department Introduction The Non-Volatile NAND Design Engineering group is responsible for the design and optimization of analog, digital and mixed-signal circuits enabling advanced NAND Flash memory products. Close collaboration with cross-functional teams ensures scalable, manufacturable, and reliable solutions across technology nodes. Position Overview As a Design Engineer in the NVE Design Engineering Core group at Micron Semiconductor Italia, you will contribute to the development of memory products that are best-in-class, using your specialized knowledge and Micron proprietary methods of designing and analyzing core and mixed circuits used in the development of memory products. Responsibilities Responsibilities include, but not limited to: • Design, simulate, and optimize NAND core circuit blocks, balancing performance, power, area, and reliability trade-offs. • Translate product and system requirements into circuit implementations, evaluating feasibility and functionality across use cases. • Perform comprehensive circuit verification (DC, AC, transient, noise, Monte Carlo, PVT corners) at block and chip level. • Collaborate with multi-functional teams to improve power efficiency, manufacturability, and overall product performance. • Develop and leverage automation solutions (e.g., Python-based workflows, AI-assisted tools) and maintain user documentation. AI Enablement and Productivity The candidate is expected to leverage AI-powered tools and data-driven methodologies to improve engineering prod

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are seeking a Senior Analog Design Engineer to join our High Bandwidth Memory (HBM) team. This role is responsible for the architecture, design, simulation, and silicon bring ‑ up of high ‑ performance analog and mixed ‑ signal circuits used in HBM PHYs and supporting infrastructure. The ideal candidate has deep expertise in high ‑ speed I/O, clocking, power management, and advanced ‑ node analog design, and has successfully delivered silicon to production. Responsibilities will include, but are not limited to: Design and own critical HBM analog circuits, including: High ‑ speed transmitters and receivers Clock generation and distribution (PLLs, DLLs, CDRs) SerDes ‑ related analog blocks Biasing, reference, and calibration circuits </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Unique Opportunities Complete ownership of verification and end to end analysis of sophisticated full chip gate level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR4,LPDDR4,DDR5 and LPDDR5 that can operate at high speeds of up to 6400MT/s. Collaborate closely with design and verification team members spread across the globe, many of whom have decades of experience in memory design. Work on multi-functional tasks that can widen your skills. Responsibilities: • Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops • Strong judgment to validate AI outputs before use (review assumptions, align with specs/standards, cross-check with simulations, waveforms, assertions, and coverage reports, and document what was accepted/changed) prior to incorporating results into design decisions, verification plans, or debug conclusions • Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Deve

Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE) — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Sr Engineer, Design — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a highly skilled and motivated Senior Design Verification Engineer to join our team. In this role, you will be responsible for the end-to-end verification of our IOMMU (Input/Output Memory Management Unit) IP. You will play a critical role in ensuring the functional correctness and performance of the design, taking ownership of the verification process right from the initial specification understanding down to final coverage closure. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have hands-on experience in ASIC or SoC verification using SystemVerilog and UVM. You enjoy debugging complex design and verification issues and working closely with cross-functional teams. You’re comfortable building verification environments from scratch and driving coverage closure. You have familiarity with standard bus protocols and modern verification tools. What We Need Experience owning block or subsystem-level verification from test planning to sign-off. Strong understanding of constrained-random verification, coverage analysis, and regression debugging. Familiarity with proto

SR ENGINEER, Design Verification — Hyderabad - Phoenix Aquila, India. Apply via Workday.

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance IP and SoC architectures for next-gen AI and compute workloads. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance-aware design. This role is hybrid, based out of Toronto, Ottawa, Boston, or Austin. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A digital design expert with a deep understanding of computer architecture and IP microarchitecture. Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows. Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals. A naturally collaborative and technical engineer — you thrive in spec definition, peer reviews, and team-wide planning. What We Need Architecture and RTL implementation of Tenstorrent’s custom IP blocks and SoC components. Performance-aware design decisions for compute, interconnect, or memory-heavy blocks. Occasional contributions to validation using emulation, FPGA prototyping, or UVM flows. Strong synthesis and timing closure awareness to support backend

Sr. Circuit Design Engineer - DRAM Design — Boise, ID - Main Site. Apply via Workday.

Sr Engineer, Advanced Packaging Design Enablement Engineering (APDEE) — Hyderabad - Phoenix Aquila, India. Apply via Workday.