Sr Solutions Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Process module ownership involving regE process characterizations and advanced process developments for 3D NAND and beyond. Work with process development engineers in Singapore and vendors to develop regE processes that meet integration requirements for next-generation 3-D NAND nodes. Transfer regE processes to high volume manufacturing (Fab10), and work on continuous improvements to manufacturability. Address specific wafer edge issues (such as bevel defects, uniformity issues), working with Fab10N team and with key business partners on tool choices for manufacturing, evaluations etc., as applicable. Focus on understanding and improving regE process margins required for meeting the mature yield goal for 3D NAND parts. Initiate and manage experiments to widen regE process margins as well as to test out manufacturability of next node solutions Incorporate best known manufac

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Together with your peers, you craft and implement our NAND-CMOS roadmap and make sure to align to product roadmaps You give directions on how to improve our device portfolio, both in performance and cost effectiveness You define, execute, and analyze silicon experiments for future device generations Interface with Design Engineers to define transistor targets, deliver transistor models, and optimize critical layout constrained Design Rules Work with TCAD simulation group to develop strategies for transistor structures to meet targets You strive to ensure that transistor models are correctly targeted to anticipate final silicon Define electrical test structures for transistors, isolation, design rule verification, and process monitoring Highly motivated to ensure transistors are developed meeting the required reliability standards You take initiative to collaborate with Manufacturing to ensure transistors are performing as expected and to debug yield/reliability issues You foster and enable a collaborative working style and team spirit by mentoring less experienced colleagues Proficiency in AI - leverage AI tools and enable Agent-AI solutions to automate yo

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . We are looking for inquisitive, well-rounded iOS engineers to join our engineering teams. Working closely with product managers, designers, and backend engineers, you’ll play an important role in enabling the newest technologies and experiences. You will build robust frameworks & features. You will empower both developers and Pinners alike. You’ll have the opportunity to find creative solutions to thought-provoking problems. Even better, because we covet the kind of courageous thinking that’s required in order for big bets and smart risks to pay off, you’ll be invited to create and drive new initiatives, seeing them from inception through to technical design, implementation, and release. What you’ll do: Build out Pinner-facing frontend features in iOS to power the future of inspiration on Pinterest Contribute to and lead each step of the pro

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath. Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis. Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments. Background in microarchitecture definition, design specification, and performance-driven trade-off analysis. What We Need Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU. Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals. Use innovative techniques to optimize power, performance, and

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . Pinterest's Data Privacy Engineering team builds access control, auditing, and data handling services and solutions used across the company to power Pinterest experiences. AI is transforming how software is built, data is analyzed, and users interact with software. We're looking for a Senior Engineer based in Dublin to help build the next generation of Data Privacy solutions for AI platforms, ensuring agents interact with data responsibly and transparently. What you’ll do: Design services and processes used to safely onboard new AI use cases Create isolated environments to enable secure agent-driven data processing without direct data exposure Design and maintain an auditing pipeline to monitor and log all AI sandbox data egress Collaborate cross-functionally with engineering teams across Pinterest to identify and tackle new data privacy c

P-1093 At Databricks, we are passionate about enabling data teams to solve the world’s toughest problems — from making the next mode of transportation a reality to accelerating the development of medical breakthroughs. We do this by building and running the world’s best data and AI infrastructure platform so our customers can use deep data insights to improve their business. Founded by engineers — and customer obsessed — we leap at every opportunity to tackle technical challenges, from designing next-gen UI/UX for interfacing with data to scaling our services and infrastructure across millions of virtual machines. And we're only getting started. The ManagedTables team at Databricks is responsible for the DataIntelligence initiatives that underpin the Unity Catalog ManagedTables offering. This encompasses products such as Predictive Optimization, Liquid Clustering, and control plane services facilitating Unity Catalog and Iceberg Rest Catalog API-based access to ManagedTables. The team is accountable for optimizing exabytes of data and saving millions of dollars annually for our customers through the Data Intelligence offerings. As part of this team, you will be working on realizing enterprise grade autonomous analytical datasystems - that ensure the best performance out-of-the-box. You will design and implement these next gen systems that leapfrog state-of-the-art: Storage lifecycle and additional background optimizations for a knob-free experience via Predictive Optimization Efficient storage structures and innovations to power storage layout solutions for the ML world Influence the Data format and Catalog interface unification efforts and enable strong ecosystem interoperability for ManagedTables The Impact you will have: Solve real business needs at large scale by applying your software engineering experience and by driving strong collaboration with Product partners Deliver a highly scalable, available, and inter-operable architecture for Managed Tables. Lo

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary As a DRAM Architect, you will optimize DRAM solutions for power, performance, and cost while pioneering new memory features and system-level innovations. You will collaborate with global, multi-functional teams to deliver high-quality, reliable, and power-efficient DRAM solutions that meet aggressive performance and time-to-market goals. Responsibilities: Develop comprehensive DRAM system/component solutions, specifications, and methodologies to optimize DRAM performance, power efficiency, and cost. Collaborate with multi-functional teams to brainstorm and implement innovative ideas, assess solution efficiency, and make necessary adjustments. Drive innovation in future memory generations within a dynamic work environment. Analyze system behavior and assess solution effectiveness, make data-driven optimizations and trade-offs. Communicate complex technical concepts to engineers from various backgrounds. Minimum Qualifications: 3&#43; years of proven experience in memory design, product engineering, or system architecture and usage Self-motivated with exceptional problem-solving skills and a drive to discover new solutions. Excellent communication and interpersonal skills. Bachelor’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field. <

About Backblaze Backblaze is the object storage leader in the open cloud movement, fueling customer success with cloud storage built purposefully to unlock budgets, unburden administrators, and unleash innovators. Together with our partners, we’re helping customers break free from the restrictive, overpriced legacy solutions that hold them back, and blaze forward with the full power of the open cloud in their hands. Founded in 2007, we scaled the business with less than $3 million in outside funding until 2021, when we did a traditional IPO on the Nasdaq stock exchange. Today, Backblaze generates over $100m in revenue and is the leading specialized storage cloud - managing over three billion gigabytes of data storage for 500K+ customers in 175+ countries, including businesses, developers, IT professionals, and individuals. But while there is a lot to celebrate in our past, there is almost as much opportunity ahead of us. We’re seeking a Sr. Software Engineer to join our team! What You'll Do: You will work on our storage platform which supports the B2 Object Storage and Computer Backup products, responsible for reliably storing the customer data. You will help improve durability, increase throughput, and drive architectural changes to support the long term requirements of our service. The Right Fit: 7+ years of OOP (Java, Rust, C++, C#, etc) in an enterprise environment (personal project work not included) Experience building large scale software systems running on thousands of servers Comfortable with all aspects of the software development lifecycle, including design, implementation, testing, and rollout Exhibits curiosity and seeks to understand before offering solutions Applies analytical thinking to ambiguous problems Bonus points for: Proficiency in Java or Rust Experience building and interpreting models, dashboards, or reports Familiarity with hard drive performance Understanding of Linux internals and file systems At this point, we hope you're feeling

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team to drive infrastructure for performance analysis, correlation and verification. You’ll work on a CPU based on RISC-V ISA, collaborating with core architects and RTL teams to deliver a highly efficient and performant design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Strong problem solver who can identify complex issues, develop practical solutions, and drive them through implementation. Enjoy building tools and improving the infrastructure, workflows, and methodologies that make CPU development more efficient. Skilled in C++ and Python, with experience using industry-standard compilation, simulation, and emulation tools. Experience with verification infrastructure and methodologies along with knowledge of high-performance CPU architecture and microarchitecture. Proficient in debugging RTL and logic across multiple design hierarchies and pre-silicon environments. What We Need Join a team driving improvements in CPU microarchitecture, verifying performance, and correlating results between RTL and the performance mode

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation AI compute. The Kernel Development and Optimization team develops the performance-critical kernels that unlock the full capability of our hardware across ML and HPC workloads. This role is hybrid based out of Belgrade, Serbia. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A strong C++ systems engineer with experience writing performance-critical or low-level software. Comfortable reasoning about concurrency, synchronization, latency hiding, and compute versus memory trade-offs. Data-driven in your approach, using profiling and benchmarking results to guide optimization decisions. Effective at debugging complex runtime or kernel-level issues in large codebases. Structured thinker who can break down ambiguous performance problems into measurable experiments. What We Need Engineers who can design, implement, and optimize GPU-style kernels such as matrix multiplication, attention primitives, and data-movement operations. Clear ownership of performance, from identifying bottlenecks to delivering measurable throughput improvements. Contribution to host-side orchestration code and parallelizati

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As Photolithography Process Development Engineer in Micron's R&D/Technology Development group, you will be responsible for process module development for memory devices, in addition to other photolithography and process integration related activities. In this position, you will work with Micron engineers, technology partners and vendors to develop unit processes that meet device requirements for next-generation semiconductors, integrate processes as part of multi-functional teams and ultimately provide technology transfers to Micron’s worldwide manufacturing network. Additionally, you will address process issues with pilot line manufacturing and work on continuous improvements for manufacturability. Advanced process development tasks will include: Performing material evaluations; reticle, layout and OPC development; process window analysis; overlay optimization. Responsibilities include, but are not limited to: Document procedures, transfer developed processes, and communicate results with senior management team and manufacturing partners Work jointly with equipment vendors to improve equipment design, test new equipment, and drive pro

P-1478 The Agentic Applications team at Databricks is on an ambitious journey to transform how we run the business. Our mission is to build resilient, in-house platforms and AI-powered capabilities that provide a genuine competitive advantage, powering our next doubling in size and revenue. As a Senior Staff Software Engineer on the Agentic Applications team, you will play a critical role delivering end-to-end applications that power our business and empower our employees with truly assistive technologies. You will be responsible for defining the technical roadmap, designing critical software systems, raising the bar on engineering excellence, mentoring junior engineers, and tackling the most challenging technical issues facing the team. You will be the technical leader for a team of software engineers. The impact you’ll have : Define the technical strategy and roadmap for building in-house solutions for critical internal workflows Partner closely with product management, design, and other engineering teams to build end-to-end, AI-powered solutions Eliminate technical risk by solving the most technically challenging issues or tackling the most complex development tasks facing the team Drive team best practices for engineering excellence, including design quality, operational reviews, testing strategies, and incident management. What we look for: 12+ years of software engineering experience, with a strong track record of technical leadership and impact. 3+ years of engineering leadership experience, serving as the technical owner for the software systems owned by your team. Experience designing and building end-to-end, full-stack cloud-native applications Customer obsession and product engineering mindset Strong communication skills and ability to influence technical and business stakeholders History of raising the engineering quality bar, focus on execution and operational rigor Strong ability to collaborate across product, engineering, and business team

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Design Verification Engineer to lead pre-silicon verification of the Beowulf SoC, with focus on the Compute Subsystem (CSS), DDR memory subsystem, and Fabric NoC. This role will drive coverage, coherency, memory traffic, connectivity, error handling, and bring-up features critical to silicon success. This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Deeply curious about SoC architecture, compute systems, DDR behavior, and Fabric NoC/interconnect verification. Expert in UVM, SystemVerilog, coverage-driven verification, assertions, and subsystem-level debug. Experienced in verifying compute subsystems, DDR controllers and PHY-facing logic, NoC/interconnect protocols, coherency, ordering, and data movement. Comfortable with reset, power management, error handling, performance, and high-concurrency system scenarios. Proactive, detail-oriented, and effective in cross-functional technical discussions. Familiar with Python, C/C++, Tcl, CocoTB, or similar verification automation tools. What We Need Develop and own scalable verification environmen

RDQ126R47 At Databricks, we are passionate about enabling data teams to solve the world's toughest problems — from making the next mode of transportation a reality to accelerating the development of medical breakthroughs. We do this by building and running the world's best data and AI infrastructure platform so our customers can use deep data insights to improve their business. Databricks Unity Catalog is the industry’s only unified and open governance solution for data and AI, built into the Databricks Data Intelligence Platform. It enables data scientists, analysts, and engineers to securely discover, access, and collaborate on trusted data and AI assets across platforms. Unity Catalog enhances productivity through AI-powered governance, simplifying compliance while maximizing interoperability. We are seeking a Senior Staff Software Engineer to lead the technical direction and development of Unity Catalog’s enterprise-grade governance capabilities. In this role, you will drive the roadmap and execution of critical features that empower organizations to govern access to their Lakehouse assets at scale. Key Responsibilities Technical Leadership : Lead the design and delivery of high-impact projects, setting standards for security, usability, performance, and scalability. Mentor senior engineers and elevate development and operational best practices across the organization. Product Ownership: Take full ownership of the Unity Catalog Governance product, driving it from initial concept to robust, scalable solutions with measurable business impact. Cross-Functional Influence: Collaborate with product and infrastructure teams to align technical strategy and execution, ensuring seamless integration and adoption of governance features. Operational Excellence: Champion the development of high-quality, reliable, and easy-to-operate software. Drive operational processes that deliver a seamless customer experience that is indistinguishable from perfect. What We Look For 15+ ye