Staff Engineer Lead Jobs

At Bazaarvoice, we create smart shopping experiences. Through our expansive global network, product-passionate community & enterprise technology, we connect thousands of brands and retailers with billions of consumers. Our solutions enable brands to connect with consumers and collect valuable user-generated content, at an unprecedented scale. This content achieves global reach by leveraging our extensive and ever-expanding retail, social & search syndication network. And we make it easy for brands & retailers to gain valuable business insights from real-time consumer feedback with intuitive tools and dashboards. The result is smarter shopping: loyal customers, increased sales, and improved products. The problem we are trying to solve : Brands and retailers struggle to make real connections with consumers. It's a challenge to deliver trustworthy and inspiring content in the moments that matter most during the discovery and purchase cycle. The result? Time and money spent on content that doesn't attract new consumers, convert them, or earn their long-term loyalty. Our brand promise : closing the gap between brands and consumers. Founded in 2005, Bazaarvoice is headquartered in Austin, Texas with offices in North America, Europe, Asia and Australia. It’s official: Bazaarvoice is a Great Place to Work in the US , Australia, India, Lithuania, France, Germany and the UK! As the Lead Engineer of Portal Reports and Insights application team, your primary responsibilities will include designing and implementing distributed, fault-tolerant systems and creating high performance Reporting and Insights applications for Bazaarvoice clients that can run nearly 10k reports every week. These reports and insights are used to produce various metrics about Bazaarvoice products and programs so that their performance can be measured. Reports can also be used to simply export raw data about client's UGC like questions, answers, reviews and products, while Insights provides an

About Vercel: Vercel is the agentic infrastructure company, freeing people and agents to ship what's next. For more than a decade we've helped builders move from idea to production with speed, security, and exceptional developer experience. Now we're scaling our products for both agents and people to ship and run software, built in the open and trusted by OpenAI, PayPal, Ramp, Supreme, and millions of developers worldwide. About the Role We're looking for a Staff level Engineer to lead the design and development of a next-generation Data Platform at Vercel. This is a unique opportunity to architect a foundational system that will power data across our products and business, supporting everything from real-time analytics to AI/ML initiatives. Reporting directly to the Senior Director of Data Engineering, you'll define the technical vision for our data ecosystem, work across the organization to align engineering strategy with product goals, and build scalable, reliable systems using modern technologies like Kafka, ClickHouse, Tinybird, and Snowflake. You'll lead from the front, writing production-grade code, setting high standards for design and data governance, and mentoring a team of engineers as the organization grows. If you're excited by the challenge of building scalable data systems that drive product innovation, we'd love to hear from you. What You Will Do Design and implement a next-generation data platform that supports diverse requirements, including batch and real-time integrations, advanced analytics, and multiple data types, leveraging Kafka, Kafka-based tooling, and additional streaming technologies to power real-time data movement and processing. Work with engineering, product, and senior leadership teams across Vercel to architect solutions that address business needs, aligning technical strategies with product goals and ensuring seamless data availability and usability. Define and maintain guidelines for data ingestion, creation, enrichment, and stor

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff Engineer: STA Methodology & Sign-off Lead We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges. This is a critical role for a forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out. The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes. Flow Development & Left-Shift Automation: Architect, deploy, and maintain adva

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Key Responsibilities Leadership Development Strategy & Program Design Design, develop, and continuously enhance leadership development programs aligned with Fab10's strategic priorities, AI-driven business and workforce transformation roadmap, and organizational capability needs. Establish a future-focused leadership development framework that equips leaders to effectively lead through AI-driven business and workforce transformation. Assess emerging business and industry trends and incorporate relevant leadership competencies into development programs. Develop leadership journeys for leaders across different levels, including emerging and new leaders, middle-level leaders, and senior leaders. Business Alignment & Organizational Capability Building Partner with Fab10 leadership teams to identify capability gaps and leadership development priorities. Translate business challenges, organizational objectives, and transformation initiatives into targeted development solutions. Ensure leadership programs support key business outcomes including operational excellence, innovation, talent development, employee engagement, and organizational effectiveness. Collaborate with internal and external experts to i

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Duties include, but not limited to: Chipping in to the development of new NAND Flash Memory by assisting with the overall design, layout, and optimization of Memory/Logic circuits Supervising and own the full chip verification activities including planning, tracking, and criteria setting Drive multi-functional team in key features evaluation and recommend decision on architecture Driving innovation into the future Memory generation with dynamic work environment Proven ability to leverage AI‑assisted (vibe) coding techniques to improve efficiency or automate design and analysis methodologies Leverage AI tools to automate the tools and workflow Applying Artificial Intelligence in workflows to improve build efficiency Successful candidates for this position will have: Broad knowledge and experience in IP Verificatipn is preferred Ability to lead multi-functional team in a project environment Good interpersonal skills with the ability to convey complex technical concepts in verbal and written form Proven knowledge of variousverification functionality on full chip level Proven expertise and background in Test Bench development in System Verilog Knowledge in verification methodologies such as UVM Knowledge of circuit simulators such as XA, hspice and/or hsim/Finesim, etc. 6-8 years of proven experience in Verification Degree or equivalent

Staff Engineer, Product Integration Lead, HIG High Bandwidth Memory — Fab 10A, Singapore. Apply via Workday.

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Title: Staff/ Senior Staff Physical Design Engineer (Technical Lead) Experience: Staff 8-10 years Senior Staff 11-13 years Location: Bangalore Hybrid/Remote or Remote in India The Role We are seeking a high-impact Staff/ Senior Staff Physical Design Engineer to serve as a Technical Lead for our next-generation silicon products. This is a "player-coach" role designed for a versatile expert who is equally comfortable architecting a convergence strategy as they are mentoring a small team of engineers. You will own the physical delivery of a major sub-chip or complex block, pushing the absolute limits of PPA (Power, Performance, Area) . As a Staff/Senior Staff lead, you are expected to be the "anchor" of the project—assertive in your decision-making, highly analytical in your debugging, and adept at managing stakeholders to ensure we hit our tape-out milestones without compromise. Key Responsibilities Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub-chip or partition. SOC clocking , FEV/VCLP specialized skills are preferred. Complex Block/Sub-chip Ownership: Take personal hands-on ownership of the most critical, high-congestion, or timing-critical blocks in the desi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a talented engineer to join our CPU design team and lead the front-end RTL physical implementation team. Drive CAD flows on multiple process technologies while working closely with core micro-architects to refine CPU core configurations and optimizing PPA. You’ll work on a CPU based on RISC-V ISA, collaborating with DV, PD, RTL and performance teams to deliver a functional, timing, and power-converged design. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An expert in physical design practices used to optimize PPA Experienced in high-performance physical design. Proficient in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation and power analysis. Skilled in synthesis, place and route tools including flows and physical design methodology. Background in CPU micro-architecture. What We Need Own front‑end physical implementation and PPA definition for a high‑performance RISC‑V CPU and CPU subsystem Work closely with microarchitects and RTL designers to “make the IP better” by optimizing frequency, power, and area

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Yield Analysis Module Lead, you will leverage advanced data analytics and deep process knowledge to identify, characterize, and quantify key yield limiters within assigned fab modules. You will lead rigorous investigative efforts to determine root causes of yield excursions, develop and publish actionable yield paretos, and translate complex data into clear technical direction for improvement. Working closely with the YA PTO team, Process Integration, and Process Engineering, you will provide accurate, data-driven guidance to the fab, influence corrective action strategies, and drive sustainable yield improvements. This role offers direct ownership of yield performance and a critical opportunity to impact continuous improvement across the manufacturing line. Lead and maintain an effective training and development program, providing coaching and mentorship to elevate team proficiency and support growth of direct reports. Proficient in Module based Data Analysis, Part Type Ownership Analysis and new part setup activities Track probe yield performance and trends to identify, characterize, and explain gaps between target and actual yields. Perform advanced data analysis to quantify yield issues and generate accurate yield paretos that guide fab priorities and improvement efforts. Apply statistical and data‑mining techniques to identify root causes and uncover opportunities for sustainable yield improvement. Collaborate closely with PI, Probe, PE, EFA, and PFA tea

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid , based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff SSD Validation Engineer at Micron Technology, Inc., you will be responsible for defining and driving comprehensive validation strategies for Micron NAND-based SSD systems and solutions. You will lead development of test plans, test cases, and automation frameworks to validate SSD firmware across functional, system-level, performance, reliability, interoperability, and customer qualification domains. You will serve as a technical leader, driving validation excellence, automation, and innovation while collaborating closely with firmware, hardware, systems, product engineering, and hyperscale customers throughout the product lifecycle. The ideal candidate will possess deep expertise in NVMe/PCIe technologies, SSD architecture, customer qualification requirements, and automated validation methodologies. This role also requires a strong focus on leveraging Artificial Intelligence (AI) and advanced automation technologies to improve validation productivity, product quality, and time-to-market. Key Responsibilities Define validation strategies, test plans, test cases, and automation frameworks for SSD firmware validation. Develop and maintain automated test solutions covering functional, system, performance, reliability, interoperability, and customer qualification requirements. Lead validation efforts across all phases of the product lifecycle, including development, qualification, customer enablement, and sustaining activities. Demonstrate strong under

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff SSD Validation Engineer at Micron Technology, Inc., you will be responsible for defining and driving comprehensive validation strategies for Micron NAND-based SSD systems and solutions. You will lead development of test plans, test cases, and automation frameworks to validate SSD firmware across functional, system-level, performance, reliability, interoperability, and customer qualification domains. You will serve as a technical leader, driving validation excellence, automation, and innovation while collaborating closely with firmware, hardware, systems, product engineering, and hyperscale customers throughout the product lifecycle. The ideal candidate will possess deep expertise in NVMe/PCIe technologies, SSD architecture, customer qualification requirements, and automated validation methodologies. This role also requires a strong focus on leveraging Artificial Intelligence (AI) and advanced automation technologies to improve validation productivity, product quality, and time-to-market. Key Responsibilities Define validation strategies, test plans, test cases, and automation frameworks for SSD firmware validation. Develop and maintain automated test solutions covering functional, system, performan

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we're building cutting-edge AI compute solutions. Developing diagnostics programs to validate the functionality and stress the performance of our solutions is a critical part of delivering exceptional products. We are looking for Engineers to join our Diagnostics Development team. These engineers will work closely with our firmware, software, board, ASIC design and verification teams to ensure that the ASICs, boards, and AI compute systems meet the highest standards of quality and performance. This role is hybrid, based out of Toronto, Canada. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You're curious, hands-on, and excited by the challenge of building powerful systems that sit at the intersection of hardware and software. You enjoy working close to the metal, whether that’s writing code, debugging hardware, or exploring how systems perform under stress. You thrive in collaborative environments and love learning from teammates across disciplines like firmware, ASIC design, and manufacturing. You’re motivated by impact and want to contribute to technology that’s shaping the future of AI and computing. What We Need A

Abbott is a global healthcare leader that helps people live more fully at all stages of life. Our portfolio of life-changing technologies spans the spectrum of healthcare, with leading businesses and products in diagnostics, medical devices, nutritionals and branded generic medicines. Our 122,000 colleagues serve people in more than 160 countries. JOB DESCRIPTION: A senior engineering professional who independently applies advanced knowledge to complete complex assignments, who leads the design and development of complex software code, unit tests and integration tests for a subsystem. MAIN RESPONSIBILITIES • Leads, is accountable for, and serves as the technical subject matter expert for the engineering design and implementation for one or more software features, identifying process issues and recommending corrective measures. • Defines feature evolution, branching, integration and deployment strategy. • Defines structure of the source code files. • Ensures successful integration. • Implements hardware/interface simulation. • Analyzes user needs, product requirements, software requirements and provides input to stakeholders Education Level Major/Field of Study or Equivalent: Bachelors Degree (± 16 years) Experience/Background Minimum 6 years Minimum 6 - 12 Years of experience The base pay for this position is $99,300.00 – $198,700.00 In specific locations, the pay range may vary from the range posted. JOB FAMILY: Product Development DIVISION: ONCO Cancer Diagnostics LOCATION:<