Staff Engineer Lead Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. • Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. We are looking for Layout Design engineer at our Micron Technology’s HBM Team in Hyderabad, India. As a Layout Design engineer, you will be working for intensive applications such as artificial intelligence and high performance computing solution, High Bandwidth Memory. As a Layout Design Engineer you will be collaborating with peer teams crossing Micron global footprint, in a multiple projects-based environment. Role and Responsibilities • Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. • Highly motivated with passion, detail oriented, systematic and methodical approach in IC layout design • Perform layout verification like LVS/DRC/Antenna, quality check and documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Demonstrate leadership Skill in planning, area/time estimation, scheduling, delegation and execution to meet project schedule/milestones in multiple project environment. • Guide junior team-members in their execu

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In this challenging role you will be engaged block level and sub-system level design and timing optimization and supervising their layout. You will be also partnering with the Logic Team to explain and support the array functionality. You will collaborate with project teams to define full-chip floorplan and how to fit and place core circuits in fullchip level. You will be also working with Technology develop to finalize array waveforms. I In addition to design activities you will be heavily engaged circuit optimization from base cells all the way to full-chip level using wide variety of simulation tools such as HSPICE, Fast SPICE and ncverilog . I In addition to design activities you will mentor junior Design to grow-up. Last but not least you are responsible for docume

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In this challenging role you will be engaged block level and sub-system level design and timing optimization and supervising their layout. You will be also partnering with the Logic Team to explain and support the array functionality. You will collaborate with project teams to define full-chip floorplan and how to fit and place core circuits in fullchip level. You will be also working with Technology develop to finalize array waveforms. I In addition to design activities you will be heavily engaged circuit optimization from base cells all the way to full-chip level using wide variety of simulation tools such as HSPICE, Fast SPICE and ncverilog . I In addition to design activities you will mentor junior Design to grow-up. Last but not least you are responsible for docume

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

We are looking to speak to candidates who are based in Gurugram for our hybrid working model. About the Role We are looking for a Staff Integration Engineer (Workato & API Integration) to join our GTMTech team. This strategic role will lead the design, implementation, and governance of enterprise-grade integrations that power our core business processes across GTM systems, with a primary focus on Workato-based integrations and modern API management patterns. You will own the architecture for critical integration domains such as Quote-to-Cash and other high-impact GTMTech programs, ensuring our integration landscape is scalable, secure, observable, and aligned with best practices for event-driven and API-first designs. You will partner with engineering, architecture, security, and business stakeholders to define standards, mentor other integration engineers, and drive continuous improvement in how we connect systems and data. The GTMTech team is focused on high-impact, large-scale technology programs, such as Quote-to-Cash. Our mission is to enhance company efficiency, boost profitability, and enable data-driven decision-making by streamlining systems, optimizing processes, and minimizing manual, low-value work through automation and AI. Key Responsibilities Lead the end-to-end architecture, design, and implementation of Workato-based integrations and APIs across GTM systems (e.g., Salesforce, NetSuite, HRIS, Google Workspace) with a focus on scalability, reliability, and security Define and evolve integration standards, patterns, and best practices, including canonical integration patterns, error-handling strategies, observability, and operational runbooks Design and review complex, event-driven integration workflows leveraging technologies such as Kafka or equivalent messaging platforms, ensuring robust handling of topics, producers/consumers, durability, and retry mechanisms Drive API-first and MCP-native design for GTM integrations, leveraging RESTful APIs al

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Contribute to the development of new product opportunities by assisting with the overall Verification Activities of DRAM Design Actively leverage AI‑based tools, agentic workflows, and automation frameworks to: Accelerate verification cycle time Assist in Test-Case/TB and various other components required for DRAM Design Verification Improve debug efficiency across simulation and silicon learning loops Provide verification support to design projects by simulating, analyzing, and debugging pre-silicon block level/full chip designs. Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features Develop and maintain test benches / test vectors using simulation tools and run regressions for coverage analysis and improvements using Agentic AI Flow Hands on experience in SV, UVM based Verification. Good scripting skills using perl, python is a plus Good understanding of digital / mixed signal circuits and experience in Digital /Mixed signal Verification. Understand the usage of industry standard tools like Virtuoso, Xcellium, Simvision, vsim, Waveview, Finseim, Hspice and Micron-specific simulators Collaborate with CAD, EDA, and software teams to integrate AI‑driven flows into simulation, verification, and design sign‑off environments and contribute to cross-group communication to work towards standardization and group success About M

Opportunity Overview: This is a unique opportunity to join a high-caliber software engineering team that is experiencing rapid growth. You’ll play a key role in building impactful healthcare technology on a modern technology stack, with a focus on our core data and AI platforms. Your work will focus on enhancing the platform's key features while also balancing scalability, reusability, and performance. As a Staff Engineer on the Application Engineering team, you’ll serve as a senior technical leader - responsible for designing and delivering high-quality, scalable software systems that power Cohere Health’s core platform. You’ll act as a multiplier, elevating the technical bar for the team, mentoring engineers, and partnering with product, data, design , clinical and payment teams to deliver solutions that meet compliance, quality, and performance standards. This role is ideal for engineers who thrive on solving complex problems in healthcare, have deep expertise in building distributed systems including data solutions, and want to influence architectural decisions for security and scale, drive cross-collaborations for alignment, establish technical standards for consistency and evolve both application and data engineering best practices at scale. What you’ll do: Technical Leadership & Architecture Define and drive the architecture of large-scale, distributed application systems across the Cohere platform. Ensure solutions are secure, performant, maintainable, and compliant with NCQA, CMS, and payer requirements. Champion platform engineering best practices in CI/CD, testing, release management, and observability. Hands-On Engineering Write clean, maintainable, and well-tested code, primarily in modern frameworks (e.g., Python, TypeScript/React, Java/Kotlin). Lead the development of core features and APIs that directly impact providers, payers, and patients. Partner with DevOps and Data teams to ensure seamless integration, scalability, and operati

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. • Identify, diagnose and resolve assembly process related problems • Coordinate and execute process, equipment and material evaluation / optimization initiatives and implement changes at process step • Lead / participate in continuous yield improvement and cost reduction activities • Validate and fan out new process baseline qualified, including new process, tools and/or materials for new product introduction • Support SPC/FDC/RMS/APC • Support site to site portability • Manage / audit material suppliers to achieve quality, cost and risk management objectives • Support internal and external audits • Utilize AI assisted tool for problem solving About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron® and Crucial® brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience. To learn more

Who are we? Cohere is the leading security-first enterprise AI company. We build cutting-edge foundation AI models and end-to-end products that are designed to solve real-world business problems. We’re training and deploying frontier models for enterprises who are building AI systems. We believe that our work is instrumental to the widespread adoption of AI and we are looking for folks that want to be part of that. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. Cohere is a team of researchers, engineers, designers, and more, who are all passionate about their craft. We are a global technology company headquartered in Toronto with key offices in London, New York City, San Francisco, Montreal, Paris, Berlin and Seoul. Join us! About the Role We're seeking a Senior/Staff Engineer to build and maintain the automation infrastructure that powers the development cycles of our North platform. This engineer will design and implement robust automation systems that enable engineers to efficiently test and validate changes across diverse environments and configurations. This role sits at the intersection of infrastructure and standards. You'll build the systems, frameworks, and culture that allow the rest of engineering to own quality themselves; improving and extending our testing platform by creating the infrastructure that allows engineers to write and execute tests, and enable every engineering team to ship with more confidence. Key Responsibilities Design and implement automation pipelines that support comprehensive testing across multiple environments with varying feature flags and realistic customer data profiles Create intelligent testing agents that simulate real user behavior to validate different configuration combinations Develop and maintain GitHub workflows and actions to automate testing, deployment, and validation processes Manage and optimize H

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description As the Facilities regional chemical engineer, you will be responsible for leading chemical system design for construction projects, providing technical support, expertise, and lead business process alignment on operational and maintenance programs for the facility chemical systems at all front and back end sites. As a global team member residing in your current site/geography, you will represent all regional facility O&M alignment initiatives. You will also lead the design for construction team and incorporate critical operational and maintenance into design for construction projects. You will work with central team on critical metrics, include eliminating production events that minimize lost moves and scrap. Responsibilities and tasks: Expert understanding of each sites bulk and specialty chemical systems operational and maintenance capabilities in order to provide critical support. <span s

About Team The IT SaaS Engineering Team is the backbone of MongoDB's go-to-market operations. We build and run the Salesforce platform — with the automation, security, and governance that Sales Operations, Revenue Operations, Security, and Compliance rely on daily to manage customer relationships and drive business growth. Role Overview We're hiring a Staff Salesforce Engineer to own the architecture, design, and evolution of our CRM platform. This role combines deep technical leadership, hands-on solution design, and a modern engineering mindset that embraces AI-powered development responsibly. As a senior individual contributor, this person sets technical direction and raises the engineering bar through architecture, design, and mentorship. What You'll do Lead architecture, design, and development of scalable Salesforce solutions — custom applications, automations, and integrations Translate business requirements into secure, maintainable, technical solutions aligned with long-term platform strategy Partner with business stakeholders, product teams, and engineering to refine requirements and deliver high-quality solutions Oversee integrations between Salesforce and other enterprise platforms, ensuring reliable data flow and sound system design Drive platform optimization across performance, scalability, usability, and governance Establish and enforce engineering standards for coding, testing, documentation, CI/CD, and release management Troubleshoot complex production issues and drive long-term, scalable resolutions Identify tech debt and drive modernization efforts across the Salesforce ecosystem Leverage AI-powered engineering tools (Apex Guru, GitHub Copilot, Salesforce Agentforce Vibes, Claude Code) to improve productivity and code quality — with strong judgment on security, privacy, and accuracy. Responsibilities Provide technical leadership through architecture reviews, design reviews, code reviews, and engineering best practices Act as a subject matter expe

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As a Global Planning Modeling Engineer, you will be a central contact for the Manufacturing network, calculating and communicating capital impacts of process changes to senior leaders in manufacturing and R&D. As a part of Operations Central Team, you will be responsible for connecting many parts of the business in order to drive execution of manufacturing and cost savings processes, including Supply Chain, Finance, Engineering, Procurement, Production and planning. Innovation is highly valued at Micron, and you will have the opportunity to develop new tools to expedite, optimize and refine the planning and reporting processes used across the network. In line with Micron's AI transformation, this role is expected to actively apply AI tools (e.g., Copilot, agents, and analytics assistants) to reimagine planning and reporting workflows, accelerate analysis, and drive productivity in an AI-enabled way of working. The ability to understand and effectively communicate capital impacts of manufacturing changes is essential. Everyday, our team has the opportunity to provide recommendations which will transform the future of manufacturing through data analysis and a global mindset. Your responsibilities will include, but are not limited to: O

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As the member of HIG HBM Package Product Engineering, you will lead and develop a high-performing team to driving Package and HBM Product engineering activities within the HBM Systems and Product Engineering Team. You will be part of a Global team of professional Product Engineers leading a portfolio of Best-In-Class Next Generation HBM Product focused on the critical KPI’s Quality, Cost, Cycle Time and Scale. You will collaborate across functions within and outside of HBM to meet both strategic and tactical objectives while continually maximizing the effectiveness of the HIG HBM PE organization. Key Responsibilities ASM Yield and DPM Improvement: Accountable for improving assembly related coverage within the manufacturing flows to improve the Time 0 and Field DPM and reduce/prevent inline fallout within the assembly process. HBM Cube Yield Improvement: Improving HBM Cube yield through test optimization and cov

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Design Verification Engineer to contribute to the unit-level verification of our RISC-V CPU front end—including instruction fetch, branch prediction, and surrounding fetch control structures. As a key individual contributor within our front-end DV team, you will focus on building testbenches, generating stimulus, and developing checkers for complex microarchitectural scenarios. This role is hybrid, based out of Austin, TX or Santa Clara, CA. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Front-End Experience: Solid background verifying CPU front-end blocks—such as instruction fetch, branch predictors (BTB, TAGE, RAS), instruction caches/TLBs, or decode—using SystemVerilog, UVM, and C++. Unit-Level Focus: Hands-on experience building clean, controllable unit testbench environments with precise stimulus and checking. Reusable Design: Pragmatic approach to building transactors, predictors, and scoreboards that can be reused across verification levels. Collaborative Problem Solver: Comfortable working alongside RTL designers to trace and fix misspeculation, redirect, and edge-case fetch bugs. What We Need Unit-Level Verifica