Substrates Supply Chain Commodity Manager Jobs

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Modeling Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for thermal modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Thermal modeling and simulation of packaging hardware to understand how heat flows from silicon test chips through various heat spreader hardware - Manage the overall integration of the packaging hardware and enable co-design between relevant stakeholders - Work closely with mechanical designers to define heat spreaders for optimal performance - Deliver and disseminate design milestones to stakeholders - Communicate designs in presentations and relevant documentation - Stay current with the latest developments in packaging technology and design techniques by attending conferences and rea

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum IC Substrate Package Layout Design Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for design of large form factor IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Design of IC substrates using Siemens Xpedition IC package design software - Work closely with stakeholders to meet design requirements - e.g., receive feedback from silicon testchip, signal integrity (SI), power integrity (PI), thermal simulation, and system integration engineers - Deliver and disseminate design milestones to stakeholders - Design validation and verification; including DRC and LVS - Advanced packaging design integration (2.5D and 3D) with IC substrate - Tapeout of designs with substrate suppliers in collaboration with Intel substrate teams - Communicate designs in presentations and relevant documentation - Stay curre

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans Intel's research divisions and partnerships with leading academic institutions worldwide. We are seeking an exceptional Quantum Packaging Signal/Power Integrity (SI/PI) Engineer to join our pioneering quantum computing team in Oregon. In this role you will be responsible for modeling and simulation of various packaging solutions from silicon redistribution layers to IC substrates within a multidisciplinary team. You'll play a crucial role in advancing Intel's silicon quantum dot technology while contributing to the development of scalable quantum systems that will revolutionize computing. Key Responsibilities - Modeling and simulation of packaging hardware including redistribution layers (e.g., interposers, RDLs), IC substrates, and silicon testchip routing - Work closely with stakeholders to meet design requirements - requirements come from both theory and hardware teams. In some pathfinding projects, you will be asked to participate in creating requirements and novel packaging hardware. - System-level modelling and simulation; end-to-end simulations to ensure designs meet system-level requirements - Deliver and disseminate design milestones to stakeholders - Communicate designs in pr

Job Details: Job Description: The Role and Impact: We are seeking a Manufacturing Quality and Reliability Engineer to join the Foundry QnR team at our Penang site, supporting Intel's advanced packaging programs (EMIB, Foveros). This role spans silicon processing and wafer-level assembly (WLA) flows, and key interfaces with packaging substrates and 2.5D EMIB technology. You will help ensure that products and processes meet rigorous quality and reliability standards from wafer fabrication through packaging and assembly. The position directly influences manufacturing performance, yield, reliability, and customer satisfaction by driving robust quality control, disciplined excursion management, and continuous process improvement. You will also have the opportunity to represent Quality and Reliability in development forums, Silicon and Advanced Packaging factory operations, and Substrate suppliers. Key Responsibilities Apply Advanced Packaging expertise to assess inline process health, excursion impact, yield risk, defect mechanisms, and downstream packaging implications. Collaborate with cross-functional teams to drive effective root cause analysis, systemic corrective and prevention actions using 8D and related problem-solving methodologies. Partner with fab manufacturing, substrates assembly, test, process engineering, and quality teams to strengthen early excursion detection, process controls, in-line screens, and outgoing quality. Drive quality control improvements devising incoming/ outgoing quality controls, using statistical process control, defect pareto analysis, control plans, audit learnings, and excursion prevention indicators across fab, substrate manufacturing, and assembly manufacturing steps. Support manufacturing excursion management, including MRB facilitation, cont

NVIDIA's GPUs and SOCs are the world leaders in power, performance and efficiency. We are continually innovating to deliver new and creative, unusual solutions to extraordinary problems in a wide range of sectors. To this purpose, we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in the world through their contributions! This position will collaborate with Technical Package Lead and different design teams in the design and development of sophisticated, detailed layout of IC substrates for NVIDIA products. In addition, work with design teams to plan schedules, resolve costs, manufacturing, and electrical design issues. What you'll be doing: As part of a Layout team, you will collaborate to implement high speed/density ASIC packages. Perform substrate breakout patterns for ASIC packages. Optimize package pinout incorporating system level trade-offs of pins assignment. Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite. Propose layout design trade-offs to the Technical Package Lead for resolution and implementation. Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance. Develop symbols and CAD library databases using Cadence APD design tools Develop methodologies to improve layout productivity What we need to see: Hold a B.S. Electrical Engineering or equivalent experience 5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology. Experience with HDI designs is a plus Proven experience in substrate layout of wire bond and flip chip packages, preferred Significant background with Cadence AP

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

Substrate Packaging Defect Metro Tool Owner — Arizona, Phoenix. Apply via Workday.

Job Details: Job Description: The Advanced Packaging Technology Development (APTD) Substrate and Wafer Assembly organization is responsible for developing cutting edge substrate packaging and wafer assembly solutions for our customers. As a member of the Substrate Technology and Manufacturing Group, you will play a critical role in enabling new manufacturing capacity across advanced packaging suppliers. In this position, you will lead substrate supplier development and qualification activities for advanced technologies such as high density FCBGA, EMIB-T and glass core substrate, ensuring suppliers achieve the required readiness to support growing customer demand. This includes driving technical enablement, managing readiness milestones, and collaborating closely with cross functional engineering teams and supplier partners. A combination of detail-oriented project management, strong technical risk assessment / problem solving skills, and effective supplier / stakeholder management will be needed to be successful. Please note: This role requires periodic evening meetings with suppliers in East Asia, as well as occasional travel to supplier sites to support essential program objectives. Key Responsibilities Define process integration roadmaps and establish manufacturing procedures to meet technology transfer milestones. Extract insights from structured and unstructured data, applying statistical analysis and coding techniques for yield improvement. Lead low yield analysis and corrective actions to address quality excursions in high-volume production environments. Drive continuous improvement initiatives to minimize defects and optimize process reliability. Assess quality and reliability risks for manufacturing material and process changes, ensuring sustained product performance. C

Who we are At Twilio, we’re shaping the future of communications, all from the comfort of our homes. We deliver innovative solutions to hundreds of thousands of businesses and empower millions of developers worldwide to craft personalized customer experiences. Our dedication to remote-first work , and strong culture of connection and global inclusion means that no matter your location, you’re part of a vibrant team with diverse experiences making a global impact each day. As we continue to revolutionize how the world interacts, we’re acquiring new skills and experiences that make work feel truly rewarding. Your career at Twilio is in your hands. . Hiring and how we work We use Artificial Intelligence (AI) to help make our hiring process efficient. That said, every hiring decision is made by real Twilions! Also, while we are a remote-first company, you may be asked to report in person on an ad-hoc basis for team gatherings, functional off-sites or customer meetings. . See yourself at Twilio Join the team as Twilio's next Software Engineer on our Data & Analytics Platform Who we are & why we’re hiring Twilio powers real-time business communications and data solutions that help companies and developers worldwide build better applications and customer experiences. Although we're headquartered in San Francisco, we have presence throughout South America, Europe, Asia and Australia. We're on a journey to becoming a global company that actively opposes racism and all forms of oppression and bias. At Twilio, we support diversity, equity & inclusion wherever we do business. About the job We are looking for a talented and experienced Software Engineer to join our Data Platform team. In this role, you will play a crucial part in designing, building, and optimizing our platform to support a wide range of data-driven initiatives. You will work closely with cross-functional teams to understand business requirements, architect scalab

EMIB-T Substrate Yield Lead — US, Arizona, Phoenix. Apply via Workday.

Category Supplier Manager, Substrate — Taichung - Fab 16, Taiwan. Apply via Workday.

Job Details: Job Description: Join Intel's Advanced Packaging Technology Development - Substrate and Wafer Assembly (ATPD: SWA) team and help us fulfill our mission to be the supplier of choice for leading-edge, cost-effective substrate packaging. As a Manufacturing Equipment Technician, you will support critical manufacturing equipment and drive continuous improvement in a highly technical, cleanroom production environment. Shift 5: Shift 5: (days frontend) AM-PM Sun-Tues and alternating Wednesday days / Hours: 6:00 a.m.-6:00 p.m. Manufacturing Equipment Technicians in Advanced Packaging Technology Development: Substrate and Wafer Assembly are responsible for: Performing electrical and/or mechanical troubleshooting to diagnose issues with non-functioning electromechanical equipment used in semiconductor manufacturing. Dismantling, adjusting, repairing, and assembling equipment according to layout plans, blueprints, operating or repair manuals, rough sketches, or engineering drawings. Performing setup, calibration, and preventive maintenance on production equipment, with a focus on wet chemistry, plating, and dry high-vacuum toolsets. Documenting maintenance activities, repairs, parts usage, and findings in accordance with established procedures and systems. Collaborating with engineering, process, and support teams to improve tool performance, reduce equipment downtime, and enhance process capability and reliability. Leading or contributing to continuous improvement projects, including root cause analysis, yield and uptime improvement initiatives, and optimization of maintenance practices. Assignments are semi-routine in nature and performed within generally defined parameters. Employees normally receive general instructions on most work and are expected to exer

About Us: AI needs a new infrastructure layer. We're building it at Modal. Every era of computing brought new workloads that previous infrastructure couldn't support: mainframes, databases, and the cloud. Each time, the company that rebuilt the layer underneath defined the decade. AI is no different, except it touches everything instead of one slice, and the window to build the layer underneath it is open right now. Our customers include category-defining companies like Lovable , Ramp , Cognition, DoorDash, and Suno. They rely on Modal for instant GPU access, sub-second container starts, and native storage, so it's simple to serve low-latency inference, fine-tune models, and access production-ready sandboxes at scale. We recently raised a $355M Series C at a $4.65B valuation, led by General Catalyst and Redpoint Ventures. We've crossed $300M+ ARR and grown fivefold since September. Our team includes creators of popular open-source projects (e.g., Seaborn , Luig i ), academic researchers, international olympiad medalists, and experienced engineering and product leaders with decades of experience. The Role Modal's LLM inference platform delivers frontier performance for open-source models with best-in-class elasticity and developer experience, made in part possible by our custom runtime with GPU memory snapshots and multi-cloud substrate . We're looking for a leader to own the direction and execution of this platform to continue to establish us as the clear market leader, working closely with customers like Cognition, Doordash, Ramp, and many more. You'll be leading a group of highly talented engineers working on our market-leading LLM inference offering, spanning the serving stack, routing infrastructure, internal agentic optimization platform, and the user-facing product surface area. This is a hands-on leadership role — expect to split your time between technical contribution, product shaping and people management depending on what the team needs. You'll set direct

Job Details: Job Description: As a Module Equipment Technician, you will play a vital role in ensuring the smooth operation of advanced manufacturing equipment used in semiconductor production. You will perform hands-on troubleshooting, maintenance, and calibration of electromechanical systems while supporting experiments and equipment modifications that drive cutting-edge advancements. Your work will directly contribute to enhancing equipment reliability and optimizing production efficiency, making an essential impact on Intel's manufacturing operations. Business Group Join Intel's Advanced Packaging Technology Development - Substrate and Wafer Assembly (ATPD: SWA) organization, a leader in delivering innovative and cost-effective substrate packaging solutions. This business group is focused on advancing Intel's capabilities in manufacturing technology to maintain competitive excellence across global markets. As part of this dynamic team, you will support critical equipment and collaborate on continuous improvement initiatives that align with Intel's broader mission of innovation and growth. Key Responsibilities Perform electrical and mechanical troubleshooting to diagnose issues with manufacturing equipment. Execute setup, calibration, corrective and preventative maintenance on production equipment, including wet chemistry, plating, and dry high-vacuum toolsets. Monitor tool performance and analyze data to identify and address equipment-related issues. Collaborate with engineering and support teams to improve equipment reliability and reduce downtime. Document maintenance activities, repair findings, and parts usage using established systems and procedures. Lead or contribute to continuous improvement projects, focusing on equipment optimization and yie