System Simulation Engineer Jobs

Job Details: Job Description: As a System Simulation Engineer, you will play a critical role in developing and optimizing simulation models to support the design and validation of cutting-edge systems. Your day-to-day activities will include creating, refining, and analyzing system-level simulations to assess performance, reliability, and functionality. Your expertise will directly contribute to the development of innovative solutions that drive Intel's success in delivering high-quality products to market. Intel Corporation is a world leader in designing and manufacturing advanced technologies that power the future of computing. The organization you will join focuses on enabling innovative engineering solutions that support Intel's broader goals of advancing technology leadership. By fostering collaboration across teams and disciplines, this group drives impactful contributions to Intel's product portfolio and technological growth. The primary responsibilities for this role will include, but are not limited to: Develop and maintain system-level simulation models to evaluate performance, reliability, and functionality. Collaborate with cross-functional teams to gather requirements and ensure alignment with design and validation goals. Analyze simulation results and provide actionable insights to improve system design and architecture. Optimize simulation frameworks for accuracy and efficiency, ensuring alignment with project timelines. Document processes, methodologies, and findings to facilitate knowledge sharing and collaboration. Qualifications: Minimum Qualifications : Minimum qualifications are required to be initially considered for this

Role Overview We are seeking a Staff Simulation Engineer to build an end-to-end aerial autonomy simulation stack at DoorDash Labs. This is a highly technical, hands-on leadership role focused on defining and implementing the simulation architecture that underpins autonomy development, validation, CI/CD testing, and pilot training. You will operate as the technical authority for simulation: owning core architecture decisions, developing key components yourself, and setting engineering standards. You will build and mentor a small, high-caliber simulation team while remaining deeply involved in implementation and system design. This role is ideal for someone who has built simulation systems from first principles, understands simulator internals deeply, and is excited to create a world-class platform from scratch. Key Responsibilities Architect and implement an end-to-end simulation stack for aerial autonomy at DoorDash Labs.. Develop high-fidelity simulation capabilities, including: Flight dynamics modeling Contact modeling and constraint handling Sensor and perception simulation Autonomy software-in-the-loop (SITL) integration Design and implement scalable simulation infrastructure to support: Regression testing in CI/CD pipelines Continuous validation of flight autonomy and autopilot software stack Mission-level testing and scenario generation Build cloud-deployed simulation systems to enable large-scale parallel testing and pilot training. Partner closely with autonomy, controls, and aircraft teams to ensure simulation fidelity and validation alignment. Establish technical direction, architecture standards, and performance benchmarks for simulation. Mentor and grow a small team of simulation engineers while remaining deeply hands-on. Required Qualifications Master’s or PhD in Computer Science, Electrical Engineering, Mechanical Engineering, Robotics, Aerospace Engineering, or a related field. 10+ years of experience in robotics or physics-based simulation. Deep expe

About the Team Our Robotics team is focused on unlocking general-purpose robotics and pushing towards AGI-level intelligence in dynamic, real-world settings. Working across the entire model stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the constraints of physical systems to improve people's lives. About the Role We are seeking a lead thermal simulation engineer to help accelerate the design and development of next-generation robotic systems through modeling, simulation, and analysis. You will work closely with mechanical, electrical, controls, and robotics engineers to evaluate designs before hardware is built, identify risks early, and guide critical architecture decisions. This role spans structural and thermal analysis and design across robotic subsystems including actuators, mechanisms, structures, electronics, and integrated systems. You will develop simulation workflows that improve engineering velocity, increase confidence in design decisions, and help us build more capable, reliable, and manufacturable robotic platforms. This role is based in San Francisco, CA. This role will be expected to be in office 4 days per week and offer relocation assistance to new employees. In this role, you will: Perform thermal simulations to assess heat generation, cooling strategies, thermal interfaces, and system-level thermal performance Partner with mechanical, electrical, and controls engineers to influence design decisions early in development Build simulation models to evaluate robotic actuators, transmissions, mechanisms, structures, soft goods, and integrated assemblies Correlate simulation results with physical testing and develop methodologies to improve model accuracy Support architecture trade studies by evaluating design concepts before hardware is built Develop simulation workflows, standards, and best practices that scale across the robotics o

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will develop and evolve the tooling ecosystem that hardware engineers rely on every day — from hardware compilers and IR transformations to simulation, debugging, and automation infrastructure. The work spans software engineering, compiler concepts, and practical hardware workflows, with direct impact on how quickly and effectively we design next-generation AI systems. You’ll collaborate closely with architects, RTL designers, and verification engineers to translate real engineering friction into durable, scalable tooling solutions. In this role you will: Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation. Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows. Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure. Work closely with designers and verification engineers to turn real pain points into durable tools. Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability. Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts. Help enable PPA optimization loops by building analysis and au

What you’ll do Be the generalist EE for the scanner system: integration, bring-up, debugging, and making the electrical side of the device reliable and serviceable. Own ultrasound experimentations that feeds the image reconstruction team Design and execute experiment setups for transducer characterization (element sensitivity, bandwidth, cross-talk mapping, beam profile measurements) and ex vivo / phantom clinical testing. Acquire, process, and analyze RF and baseband signals for data quality assessment and benchmarking. Design simple boards and adapters as needed (monitoring, power/safety, interface/conditioning), and take them from prototype through a stable revision. Prototype quickly, then harden what works: wiring/harnessing, grounding, safety interlocks, and reliable integration across subsystems. Own practical test setups and documentation (fixtures, scripts, procedures) that make experiments repeatable and results comparable over time. What we’re looking for Strong hands-on EE background with experience building, debugging, and iterating on real systems in the lab. Solid understanding of signal processing fundamentals — knows what to measure, how to condition and digitize it, and how to evaluate signal quality in the context of an imaging system (SNR, bandwidth, dynamic range, artifacts). Comfortable spanning system integration + occasional design work (schematics/layout reviews or light PCB design) in a fast-moving environment. Ability to work at the boundary between hardware and algorithms: measure reality, communicate constraints, and help close gaps vs simulation. High agency and practicality: able to set up experiments, get trustworthy data, and unblock others on a lean team. Useful experience Analog/mixed-signal, or high-speed data capture experience; strong instincts for instrumentation and noise/debugging. Ultrasound or acoustic sensor handling: hydrophone calibration and field mapping, transducer impedance characterization, element-level sensitivity

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role As a software engineer on the Scaling team, you’ll help build and optimize the low-level stack that orchestrates computation and data movement across OpenAI’s supercomputing clusters. Your work will involve designing high-performance runtimes, building custom kernels, contributing to compiler infrastructure, and developing scalable simulation systems to validate and optimize distributed training workloads. You will work at the intersection of systems programming, ML infrastructure, and high-performance computing, helping to create both ergonomic developer APIs and highly efficient runtime systems. This means balancing ease of use and introspection with the need for stability and performance on our evolving hardware fleet. This role is based in San Francisco, CA, with a hybrid work model (3 days/week in-office). Relocation assistance is available. In this role, you will: Design and build APIs and runtime components to orchestrate computation and data movement across heterogeneous ML workloads. Contribute to compiler infrastructure, including the development of optimizations and compiler passes to support evolving hardware. Engineer and optimize compute and data kernels, ensuring correctness, high performance, and portability across simulation and production environments. Profile and optimize system bottlenecks, especially around I/O, memory hierarchy, and interconnects, at both local and distributed scales. Develop simulation infrastructure to validate runtime b

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for signal integrity (SI) system design engineers who have a deep expertise in the SI area, and hold strong system level design knowledge This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Lead system signal integrity (SI) design for AI supercomputer product in the data center application. Collaborate with chip, package, boards, rack and system engineers, design partners to drive system SI design and develop innovative interconnect and high-speed technologies Identify and evaluate new technologies and methodologies to improve signal and power integrity in product design, and contribute to the development of new products and technology by providing expertise in signal integrity Perform simulation and modeling to identify and troubleshoot signal integrity issues Lead system interconnect design, bring up and qualification As the scope of the role and team grows, understand and influence roadmaps for hardware partners for our datacenter networks, racks, and buildings. You might thrive in this role if you: Have at least 10 years of industry experience, including experience design hardware system and SerDes testing for data center applications Have a strong bias toward action, and won’t take no for an answer. Have experience and good knowledge of system design experience in the SI areas, from chip, SerDes, board, rack level Have ex

About the Team: OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators. You will play a key role in verifying complex hardware systems—ranging from individual IP blocks to subsystems and full SoC—working closely with architecture, RTL, software, and systems teams to deliver reliable silicon at scale. In this role you will: Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality. Define verification plans based on architecture and microarchitecture specs. Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies. Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness. Drive bug triage, root cause analysis, and work closely with design teams on resolution. Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments. You might thrive in this role if you have: BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification. Proven success verifying complex IP or SoC designs in industry-standard flows Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi). Strong knowledge

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role You will build the low-level device runtime that turns compiled programs into efficient, functional and performant execution on OpenAI’s custom AI accelerator. This software will schedule kernel launches, manage device memory and address spaces, coordinate synchronization, and expose reliable abstractions to higher-level runtimes and frameworks. You will work at the boundary of software and hardware, partnering with compiler, kernel, architecture, verification, and silicon teams to define interfaces and validate behavior. You will also use and improve event-based, cycle-accurate simulation to develop runtime capabilities before silicon is available, diagnose performance and correctness issues, and guide hardware-software co-design. In this role, you will: Design and implement the low-level device runtime for OpenAI custom silicon. Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling. Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetime across concurrent workloads. Implement synchronization primitives, events, barriers, streams, and ordering guarantees that are correct and efficient. Define clean interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems. Use event-based, cycle-accurate simulators to develop, validate, debug, and performance-tune runtime behavior before and after silicon availability. Di

Work Flexibility: Onsite It's Time to Join Stryker! Stryker is seeking a Staff Electrical Engineer to support the design and development of electrical systems and subsystems for complex medical devices. In this role, you will apply your electrical engineering expertise across design, prototyping, testing, troubleshooting, and documentation. You will translate product and customer needs into engineering requirements and robust electrical designs while collaborating closely with cross-functional teams throughout the product development lifecycle. What You Will Do Electrical Design and Development Design and develop electrical components, circuits, and subsystems for medical devices. Translate design inputs and system requirements into electrical engineering specifications and detailed designs. Develop, evaluate, and refine design concepts through analysis, prototyping, simulation, and bench testing. Apply advanced electrical test methods to evaluate component and subsystem performance. Investigate complex technical problems, identify potential solutions, and evaluate design alternatives against product and subsystem requirements. Conduct technical research, analysis, and engineering studies to support design decisions and product development. Assess system-level impacts and dependencies associated with electrical design choices. Verification and Technical Execution Develop and execute test methods to evaluate electrical designs, components, and subsystems. Analyze test results, troubleshoot design issues, and drive problems to root cause and resolution. Apply engineering analysis, modeling, simulation, and statistical methods as appropriate to support design decisions. Partner with other engineering dis

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. Role Overview We are seeking an experienced ASIC Package Signal Integrity / Power Integrity Engineer to drive electrical architecture, modeling, optimization, and validation for the most advanced AI/HPC silicon and package design. This role focuses on high-speed SerDes and memory channel architecture, advanced 2.5D/3D package SI/PI, substrate to package co-design, power-delivery-network optimization, electromagnetic modeling, and simulation-to-measurement correlation. The ideal candidate has strong hands-on experience with high-speed channel and PDN analysis across ASIC packages, interposers, substrates, and power-delivery structures, and can translate simulation results into practical design requirements for interposers and package substrate design optimization. The engineer will work closely with ASIC, package, system, mechanical, thermal, power, and silicon validation teams from early architecture and feasibility studies through production bring-up. In this role you will Own SI/PI architecture and analysis for advanced AI ASIC packages from early feasibility studies through production. Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces. Perform package, interposer and substrate modeling using 2D/3D electromagnetic solvers. Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps based on SI/PI re

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will ensure functionality and performance of the system. This role is based out of Tokyo, Japan and offer flexible Hybrid work style. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Responsibilities: Verify Tenstorrent’s digital IP and SoC logic at chiplet integration level, using industry standard verification methodologies Build and improve components of verification infrastructure including model builds and simulation/regression runs, Create verification components like testbenches, checkers and test generators, Add assertions and coverages along associated methodologies, Build verification test plans for subsystems, align them with project stakeholders, implement test suites, summarize the results and share feedback with project stakeholders Publish and review verification metrics and drive

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

About the Team DoorDash Labs is an independent team within DoorDash. We explore robotics and automation to transform last mile logistics in the long term. If you have a passion for applying robotics solutions in a service used by millions of people, then we want to talk to you! About the Role We are hiring a Firmware Validation & Integration Engineer for our autonomy software team. This is a critical role to build robust and scalable validation for our firmware and systems to ensure reliability at every level. In this role, you will work with our electrical, firmware, and autonomy engineers to build the infrastructure and test suites required to validate the system. This includes designing and implementing our Hardware-in-the-Loop (HIL) simulation environments and automation frameworks from the ground up. You will report to the Autonomy Platform Lead on our Autonomy Platform Team at DoorDash Labs. We expect this role to be hybrid with some time in-office and some time remote. You’re excited about this opportunity because you will… Play an integral role on a small and focused team. Design and build Hardware-in-the-Loop (HIL) systems to simulate vehicle dynamics and sensor data for comprehensive firmware and system-level validation. Develop automated test infrastructure and software tools to exercise multiple embedded platforms throughout our robot system. Interface many layers of our control system including vehicle controls, power management, and motion control to ensure seamless system integration. Implement low-level test sequences and validation algorithms to safely stress-test vehicle components such as batteries, drive-train, and thermal management devices. Collaborate with cross-functional teams to identify edge cases and hardware-software corner cases that impact vehicle safety and performance. We’re excited about you because… BS/MS degree in Computer Science, Robotics, Electrical Engineering, or related technical field. 5+ years of experience in validati

Join the NVIDIA's Solutions Engineering team that is reshaping the future of driving! Our goal is to build and deploy scalable solutions for autonomous vehicles and as a result, create safer and more efficient roads. Our team is hands-on, passionate about practical results, and values diversity. You will help craft the application software architecture by working closely with external partners developing on our platform and on collaborations across multiple teams within NVIDIA working on autonomous vehicles. You will also advance and refine the overall drivability of our solution, focusing on integration challenges and using your deep analytical skills to tease through the complexity of the system to find effective solutions. NVIDIA is widely considered to be one of the technology world’s most desirable employers, and is committed to fostering a diverse work environment and proud to be an equal opportunity employer. If you are passionate in bringing autonomous vehicles into the world and see the solution come together, we would like to hear from you! What you'll be doing: Shape the application architecture internally, with a focus on perception & sensor fusion, by collaborating closely with architecture and software development teams. Integrate and adapt NVIDIA solutions in target vehicles, ensuring that both perception and sensor fusion are adapted and tuned to meet the desired driving performance and functionality. Lead bring-up activities and provide technical support to resolve functional and perception & sensor fusion related issues. Perform and leverage in-vehicle and simulation test drives for functional and performance analysis on the recorded data. Work with our partners to efficiently integrate hardware and software components, understand the system architecture, profile performance, identify bottlenecks, and drive optimization <