Verification Director Jobs

WPP is the trusted growth partner for the world’s leading brands. We unite cutting-edge media intelligence and data solutions, world-class creativity, next-generation production, transformative enterprise solutions and expert strategic counsel in a single company – powered by exceptional talent and our agentic marketing platform, WPP Open, to help our clients navigate change, capture opportunity and deliver transformational growth. We work with the world's most valuable brands and have global reach across 100+ markets, with deep local expertise. Our people are the key to our success. We're committed to fostering a culture of creativity, belonging and continuous learning, attracting and developing the brightest talent, and providing exciting career opportunities that help our people grow. For more information, visit WPP.com. Job Summary - To manage travel and expense reimbursement of employees in an organization and ensure timely payments of all expense claims. Key responsibilities - Educate employees about travel program policies and correct procedures. Verification of T&E Expense claims in Macanomy. Reconciliation and Clearing of T&E GL accounts and month end accrual reports. Posting of Macanomy claims and preparing Reconciliation file and sharing with the Payment team. Employee profile creation and Modifications. Service now tool query handling. Monitoring generic mailbox and follow up with employees. Amex reconciliation file and sending inputs to process payments as per deadlines. Monitoring Generic Mailbox. Report generation and Allocation within the team on daily basis. Skills/Experience Minimum 4-6 years of experience in Travel & Expense – Accounts Payable. Bcom Graduate. Should be an experienced problem solver with excellent written and verbal communication skills. Flexible attitude to achieve results. Excell

About Pinterest: Millions of people around the world come to our platform to find creative ideas, dream about new possibilities and plan for memories that will last a lifetime. At Pinterest, we’re on a mission to bring everyone the inspiration to create a life they love, and that starts with the people behind the product. Discover a career where you ignite innovation for millions, transform passion into growth opportunities, celebrate each other’s unique experiences and embrace the flexibility to do your best work. Creating a career you love? It’s Possible. At Pinterest, AI isn't just a feature, it's a powerful partner that augments our creativity and amplifies our impact, and we’re looking for candidates who are excited to be a part of that. To get a complete picture of your experience and abilities, we’ll explore your foundational skills and how you collaborate with AI. Through our interview process, what matters most is that you can always explain your approach, showing us not just what you know, but how you think. You can read more about our AI interview philosophy and how we use AI in our recruiting process here . tvScientific is the first and only CTV advertising platform purpose-built for performance marketers. We leverage massive data and cutting-edge science to automate and optimize TV advertising to drive measurable business outcomes. Our solution combines media buying, optimization, measurement, and attribution in one efficient platform, built by industry leaders with deep roots in programmatic advertising, digital media, and ad verification, now purpose-built for CTV performance advertisers can trust. As a Sr. Lead Client Partner, you’ll leverage your experience in performance marketing and digital advertising to champion the value of our product, empowering brands, companies, and agencies to achieve their advertising objectives through the power of CTV. Day to day, you'll strategically manage named account lists (NALs) within your industry vertica

Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies—from the world's largest enterprises to the most ambitious startups—use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies - from the world’s largest enterprises to the most ambitious startups - use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team The Product Design team defines and delivers user-facing experiences across Stripe. Product Designers work closely with engineers, product managers, researchers, strategists, operations, data scientists, and marketers to shape products from early strategy through launch and iteration. You'll join the Risk team, where design shapes how businesses get started on Stripe, stay compliant, and grow with confidence. Stripe's ability to innovate, expand globally, and serve the world's most ambitious companies depends on world-class risk management. But great risk management requires clear, trustworthy, and surprisingly well-crafted experiences during some of the most important moments in a user's relationship with Stripe. From onboarding and verification to account health, your work will help users understand what's happening, know what to do next, and feel confident that Stripe is growing with them as a trusted partner. Risk at Stripe is also ev

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities: Develop and standardize EMIR methodology that applies consistently across all DRAM products, ensuring alignment, repeatability, and high-quality analysis outcomes Perform static and dynamic EM/IR and PDN analysis using RedHawk or Totem or other industry‑standard tools; identify root‑cause issues such as high‑resistance segments, insufficient via density, and decap deficiencies, and provide clear, actionable recommendations to design and layout teams. Actively leverage AI‑based tools, agentic workflows, and automation frameworks for effective Power-delivery-network (PDN) analysis. Maintain a strong understanding of the full EMIR flow—from netlist preparation, extraction, simulation, and debug to reporting and silicon correlation—and ensure accurate evaluation across operating modes and temperatures. Partner across design, timing, physical implementation, architecture, modeling, and verification teams to understand real switching behavior, develop worst‑case vectors, and standardize analysis expectations across global teams. Collaborate with cross-geographical teams and also EDA tool vendors to evaluate and improve EMIR methodologies, and document Best Known Methods (BKMs) to enhance consistency and correlation across DRAM teams. Develop and maintain dashboards to track EMIR results, monitor trends, and support signoff progression for multiple designs. Qualifications: Master’s degree i

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. What’s Encouraged Daily: AI-First Engineering: Deploy AI tools (LLMs, code/RTL generation, spec parsing, waveform interpretation, layout engines) as default practice. Continuously identify automation opportunities and rearchitect workflows—specs, simulations, reviews, hand-offs—to be AI-consumable. Build prompt libraries, agents, and scripts that eliminate recurring manual patterns! AI Leadership: Champion AI adoption by evaluating emerging tools, running pilots, and publishing standard methodologies that measurably reduce cycle time or prove quality! Technical Ownership: Design and verify major IO/datapath blocks (receivers, serializer, clock distribution, equalizers, ZQ calibration, ONFI training, wave pipelines) to meet performance specs, using AI to accelerate exploration, sizing, and verification. Multi-functional Collaboration: Work with integration, design, and Apps teams to define interfaces and evaluate new specifications. Use AI to summarize discussions, reconcile specs, and quantify trade-offs. Mentorship: Document AI-augmented methodologies and teach engineers to work in an AI-first environment—not just which tools to use, but how to rethink engineering with AI. Minimum Qualifications: BS/MS in Electrical Engineering with 8+ years IC design experience Hands-on AI tool usage (LLM assistants, coding copilots, agentic workflows, ML-based EDA) with concrete examples of productivity or design impact Experience redesig

Who We Are Addepar is a global data and AI platform empowering investment professionals to turn complex financial information into actionable intelligence. Addepar unifies portfolio, market and client data in a total portfolio view and delivers AI-powered insights within investment and client workflows. More than 1,500 firms in 60 countries use Addepar to manage and advise on nearly $10 trillion in assets. Its open platform integrates with 650 software, data and consulting partners to power end-to-end investment operations across firms of all sizes and levels of complexity. Addepar supports clients worldwide with offices in New York City, Salt Lake City, São Paulo, London, Edinburgh, Geneva, Warsaw, Dubai, Pune and Singapore. The Role As part of the broader Addepar Data Management & Quality organization, the Data Client Support team is responsible for ensuring our customers receive first-class support experience and are able get the most value out of their data in Addepar. The Data Client Support team sits at the nexus of Addepar's activity and requires daily communications with clients, data providers, and other personnel across the company. Important : This role requires for you to be in office 3 days per week in Pune. Applicants must have legal authorization to work in the country where this role is based on the first day of employment. Visa sponsorship is not available for this position. What You’ll Do Address client inquiries related to Addepar’s portfolio data feeds and on general data product functionalities within established SLAs. Manage and complete requests from internal Data teams that require client outreach and/or action to resolve data verification issues. Investigate client reported bugs and data processing issues, and triage with Engineering & Product when needed. Partner with Account Managers, Solutions Architects, and other members of GTM to drive alignment on data related escalations and ensure positive outcomes for clients. P

About the Role The Mechanical Commissioning Project Engineer owns mechanical commissioning planning, readiness, quality coordination, and test execution oversight for the project. This role ensures mechanical systems are installed, inspected, started, balanced, controlled, and tested in a way that supports reliable integrated facility performance. Reports to the Commissioning Project Lead and partners closely with mechanical contractors, equipment vendors, design/engineering teams, the electrical commissioning lead, controls stakeholders, and vendor field/test engineers. Key Responsibilities Develop and maintain the mechanical commissioning scope, readiness criteria, inspection strategy, and discipline test execution plan. Review mechanical design packages, specifications, submittals, method statements, controls narratives, sequence assumptions, and testing requirements for commissionability and risk. Coordinate mechanical QA/QC inspections with contractors and vendor field/test engineers, including installation checks, pre-functional readiness, deficiency capture, and closeout tracking. Own mechanical commissioning procedure development and review, including equipment startup, functional testing, controls verification, balancing prerequisites, failure mode validation, and integrated systems testing inputs. Coordinate with equipment vendors on factory/site acceptance requirements, startup support, test prerequisites, documentation packages, and vendor participation during critical tests. Support readiness and execution for cooling, ventilation, hydronic, pumping, heat rejection, controls, and other project-specific mechanical systems. Lead discipline-level review of mechanical test results, deficiencies, corrective actions, retest requirements, trend logs, and acceptance evidence. Maintain mechanical commissioning dashboards and status inputs for the Commissioning Project Lead, including risk items, resource needs, test readiness, and issue aging. Partner with the E

About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We are looking for a highly experienced RTL engineer to own critical on- and off-chip interconnect components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip communication fabrics connecting high-bandwidth compute, memory, and I/O subsystems as well as purpose-built off-chip interfaces and protocols needed to enable custom computing at scale. This is a senior, hands-on engineering role with broad technical ownership. You will drive design from requirements through the full silicon lifecycle, from architecture definition and performance analysis through RTL implementation, verification closure, physical design convergence, bring-up, and production readiness. You will plan and oversee the work of junior engineers and help drive and develop productive engineering relationships with external partners and help manage partner execution. This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees. In this role, you will: Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces. Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and de

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. Snowflake is about empowering enterprises to achieve their full potential — and people too. With a culture that’s all in on impact, innovation, and collaboration, Snowflake is the sweet spot for building big, moving fast, and taking technology — and careers — to the next level. ABOUT THE ROLE: You will work on critical business initiatives in the core database engine, bring an AI-forward approach to software development and accelerate roadmap cycles for the benefit of our customers. Your work will directly impact how developers and businesses build with data. You'll own the full AI engineering lifecycle: design, prompt/tool engineering, evals, deployment, measurement, and optimization. You'll work with a small, high-powered engineering team. What you will do in this role: Own features end-to-end for Snowflake Database Engineering products. Build agentic workflows, coding harnesses, evaluation pipelines. Build enterprise-grade context engineering: function calling, tool schemas, guardrails, agent teams, and verification/repair. Design evals and hillclimb : create golden sets, create rubrics and metrics, analyze errors, run experiments to hill climb on the metrics. Partner with product and infra: translate customer problems into products and experiments. Collaborate with infr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Physical Design Engineer-DPG-LPDDR at Micron, you will work on innovative memory and storage solutions. These solutions help transform data into intelligence quickly. You will join a dedicated team collaborating to develop world-class products that set industry standards. Key Responsibilities Lead end-to-end RTL-to-GDSII implementation for complex SoCs across advanced technology nodes. Drive floor planning, power planning, CTS, place & route, timing closure, and physical signoff. Own PPA optimization, low-power implementation, congestion management, and design convergence. Lead STA, SI, EM/IR, DRC, LVS, and reliability closure to achieve tape out readiness. Define physical design methodologies, automation strategies, and flow improvements. Partner with Architecture, RTL, DFT, Verification, CAD, and Product Engineering teams to resolve complex implementation challenges. Provide technical leadership, mentor engineers, and drive execution across global teams. Hands-on custom layout design experience is a strong value-added skill, enabling analog/mixed-signal integration, layout optimization, and advanced-node design challenges Leverage Artificial Intelligence (AI) tools to improve RTL-to-GDSII design productivity, quality, and turnaround time. Drive adoption of Generative AI and Agentic AI solutions for physical design automation, design closure, and engineering workflow optimization. <p

At Jamf, we believe in an open, flexible culture based on respect and trust. Our track record and thriving work environment all stem from the freedom we grant ourselves to get the job done right. We take pride in helping tens of thousands of customers around the globe succeed with Apple. The secret to our success lies in our connectivity, while operating with a high degree of flexibility. Work-life balance remains our priority while feeling connected is important to maintain our strong culture, achieve our goals, and thrive as #OneJamf. This role is offered as a hybrid in Brno, the Czech Republic . We are only able to accept applications for those based in the Czech Republic or who have sponsorship to live and work in the Czech Republic . What you'll do at Jamf : At Jamf, we empower people to be their best selves and do their best work. As a Software Engineer II on a new team enabling secure, governed adoption of autonomous and agentic workflows, you'll help build production systems where AI agents do real work on real code - authoring changes inside deterministic gates, with independent verification and a full audit trail. This is a greenfield build inside a mature platform, starting with Security. What you can expect to do in this role: Build the production systems where AI agents do real work on real code – authoring changes that run inside deterministic gates, with independent verification and a full audit trail behind every one. Take customer and platform problems, break them into workable pieces with your agile team, and own most of them end to end. Draw the line on autonomy: design the trust boundaries, blast radius, and least-privilege model for the automation itself, which holds elevated access to production. Build the evaluation and observability that keeps non-deterministic systems honest – measuring accuracy and catching silent degradation before anyone else

At Jamf, we believe in an open, flexible culture based on respect and trust. Our track record and thriving work environment all stem from the freedom we grant ourselves to get the job done right. We take pride in helping tens of thousands of customers around the globe succeed with Apple. The secret to our success lies in our connectivity, while operating with a high degree of flexibility. Work-life balance remains our priority while feeling connected is important to maintain our strong culture, achieve our goals, and thrive as #OneJamf. This role is offered as a remote in Poland . We are only able to accept applications for those based in Poland or who have sponsorship to live and work in Poland . You may be required to work periodically at a Jamf office or collaborative work location with other Jamf employees in your area for certain events or moments that matter. What you'll do at Jamf : At Jamf, we empower people to be their best selves and do their best work. As a Software Engineer II on a new team enabling secure, governed adoption of autonomous and agentic workflows, you'll help build production systems where AI agents do real work on real code - authoring changes inside deterministic gates, with independent verification and a full audit trail. This is a greenfield build inside a mature platform, starting with Security. What you can expect to do in this role: Build the production systems where AI agents do real work on real code – authoring changes that run inside deterministic gates, with independent verification and a full audit trail behind every one. Take customer and platform problems, break them into workable pieces with your agile team, and own most of them end to end. Draw the line on autonomy: design the trust boundaries, blast radius, and least-privilege model for the automation itself, which holds elevated access to production. Build the evaluation and observability

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary Micron is seeking a Principal Physical Design Engineer to provide technical leadership for advanced DRAM digital design implementation and signoff methodologies. This role will drive physical design execution from RTL through tapeout, with a strong focus on timing closure, power integrity, EMIR analysis, and design reliability. The engineer will collaborate across architecture, RTL, implementation, CAD, and technology teams to develop scalable physical design solutions that achieve power, performance, area (PPA), and reliability targets for next-generation memory products. Additionally, this individual will lead methodology innovation, mentor engineers, and influence the future roadmap for physical design and power integrity across the organization. Responsibilities Lead physical design implementation of complex DRAM digital designs, including floorplanning, place and route, clock tree synthesis, timing closure, and tapeout activities. Drive power integrity strategies and signoff methodologies, including PDN planning, IR drop analysis, electromigration (EM) verification, and EMIR signoff. Collaborate with multi-functional teams to resolve timing, congestion, power, signal integrity, and reliability challenges at both block and full-chip levels. Develop and deploy methodology improvements, automation solutions, and guidelines to improve build quality, efficiency, and scalability. Mentor engineers and provide technical leadership while influencing future memory products t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary: We are looking for a skilled and detail-oriented Quality Engineer – MEP to ensure the highest standards of quality and compliance in mechanical, electrical, and plumbing systems across industrial and cleanroom construction projects. The ideal candidate will have extensive hands-on experience in CS/MS/SS piping works, clean process gas and ultra-pure water piping, ducting, firefighting, and underground utility systems, along with a deep understanding of QA/QC procedures, welding standards, and international codes (ASME, IS, ASTM). This role demands a strong foundation in P&ID and PFD interpretation, cleanroom construction quality checks, and MEP systems validation, particularly within Semiconductor, Pharmaceutical, or High-Tech Manufacturing environments. Key Responsibilities: • Implement and monitor Quality Assurance and Quality Control (QA/QC) systems for all Mechanical, Electrical, and Plumbing (MEP) works. • Conduct inspection and quality verification for carbon steel (CS), mild steel (MS), and stainless steel (SS) piping systems including welding, fit-up, and joint integrity. • Supervise and validate quality of clean process gas and ultra-pure water (UPW) piping systems, ensuring compliance with cleanliness and fabrication standards. • Perform orbital welding quality checks, review weld logs, and ensure compliance with approved WPS, PQR, and WPQ documentation. • Review and monitor installation of ducting, firefighting networks, DICL underground pipi

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry. As a Static Timing Analysis (STA) Engineer — you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out. This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation. Key Responsibilities Responsibilities will include, but are not limited to: Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions. Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.