Advanced Operations Engineering Graduate Program in United States

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Title: Nurse Practitioner, Advanced Practice Provider Company: Oak Street Health Location: 700 Nebraska Ave, Kansas City, KS 66101 Hours: Full-time, Monday-Friday, 8am5pm Salary: $129,000 - $148,000 *Wider range available depending on experience and location Role Description: The purpose of a Nurse Practitioner at Oak Street Health is to provide effective and equitable value-based primary care to adults on medicare to keep them happy, healthy, and out of the hospital. Nurse Practitioners see patients independently and collaborate with physicians, depending on the patient’s specific situation. Nurse Practitioners provide longitudinal care and build meaningful patient relationships; this creates trust and helps our patients understand and feel connected to their care plan. Nurse Practitioners practice in our outpatient practices on a collaborative care team composed of a physician, nurse practitioner or physician assistant, medical assistants, a dedicated medical scribe, and support from registered nurses and care managers. We partner with a network of elite specialists and hospitals for specialty and acute care. As such, our healthcare providers can focus on care within the clinic: primary care, care coordinati

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Advanced Packaging Technology Development (APTD) team at Micron is shaping the future of memory and storage technologies that fuel the AI era. We collaborate with global R&D groups, suppliers, and manufacturing teams to turn bold ideas into production-ready solutions. We innovate fast, learn continuously, and work as one team! This position is intended to be part of Micron's Technical Leadership Program (TLP). This is a career path for individuals seeking to advance as technical leaders and industry innovators. TLP members are expected to influence, lead, and mentor others. Position Overview: We are seeking an experienced organizational leader who will l ead and influence methodology improvements, including best practices in process development, data-driven decision-making, and application of AI/advanced analytics to drive innovation. In this role, you will drive strategic process development for Micron’s most advanced memory products, including HBM, 3DS DRAM, and emerging 3D architectures. You will guide end‑to‑end technology execution, partner across organizations, and influence both internal roadmaps and the external ecosystem. This is a high-impact role for someone who thrives at the intersection of innovation, complexity, and collaboration. Responsibilities: Own advanced packaging process technologies across wafer‑level and die‑level modules from pathfinding through manufacturing readiness Develop

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Title: Nurse Practitioner, Advanced Practice Provider Company: Oak Street Health Role Description: The purpose of a Nurse Practitioner at Oak Street Health is to provide effective and equitable value-based primary care to adults on medicare to keep them happy, healthy, and out of the hospital. Nurse Practitioners see patients independently and collaborate with physicians, depending on the patient’s specific situation. Nurse Practitioners provide longitudinal care and build meaningful patient relationships; this creates trust and helps our patients understand and feel connected to their care plan. Nurse Practitioners practice in our outpatient practices on a collaborative care team composed of a physician, nurse practitioner or physician assistant, medical assistants, a dedicated medical scribe, and support from registered nurses and care managers. We partner with a network of elite specialists and hospitals for specialty and acute care. As such, our healthcare providers can focus on care within the clinic: primary care, care coordination, and population health. Core Responsibilities: Provision of exceptional primary care. Conduct office visits for routine and acute issues. Administer Annual wellness visits and health risk assessments, which require a holistic v

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: We are advancing the future of semiconductor packaging through innovative 2.5D, 3D, and heterogeneous integration technologies. Our team develops the processes that enable next-generation AI and high-performance computing products, working across materials, device, design, manufacturing, and test engineering to solve complex technical challenges. If you're excited by emerging packaging architectures and breakthrough integration approaches, you'll find meaningful opportunities to make an impact here. Position Overview: As a Process Integration Lead for Advanced Packaging, you will lead a team focused on developing and integrating advanced packaging technologies from concept through full-scale manufacturing. This role plays a critical part in enabling high-performance multi-die solutions by driving technology development, process integration, technology transfer, and collaborative execution. You will help shape the roadmap for next-generation packaging platforms while mentoring a highly skilled technical team. Responsibilities: Manage and grow a team responsible for seamless process integration across 2.5D and 3D packaging platforms, including advanced interconnect architectures, die-stacking solutions, and HBM implementation. Spearhead the development, optimization, and qualification of emerging packaging technologies through experimental design (DOE), process analysis, performance validation, and establishment of design rules. Improve

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Technical Strategy & Innovation Define and execute the technical roadmap for Advanced DRAM Films development. Provide technical leadership across Epi, device films, hardmask technologies, HAR deposition, and diffusion processes. Drive innovative process solutions that enable future technology nodes while meeting manufacturability, yield, reliability, and cost objectives. Partner with Process Integration and cross-functional teams to resolve critical technology challenges. Leverage Artificial Intelligence to enhance problem solving across technical and logistical spaces. Organizational Leadership & Team Development Lead, coach, and develop a growing organization of engineers, technical leads, and future managers. Foster a culture of technical excellence, innovation, accountability, collaboration, and ownership. Develop talent through mentoring, succession planning, talent management, and strategic hiring. Create an environment that accelerates learning, encourages technical curiosity, and enables career growth for engineers at all levels. Drive high levels of team member engagement by cultivating an inclusive, supportive, and high-performing culture where employees feel valued, empowered, and connected to Micron's mission and business objectives. Champion employee development, recognition, feedback, and wellbeing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Overlay Strategy, Roadmap & Technical Leadership Own the overlay roadmap including bond overlay technologies. Serve as the technical authority for overlay, defining overlay specifications, error budgets, mark strategies, technical signoff criteria, and scaling requirements for future technology nodes. Develop innovative overlay solutions that enable advanced bonding while meeting performance, yield, manufacturability, and scaling objectives. Drive advancement of overlay metrology, automation, process control, modeling, and analytics capabilities in partnership with Process and Metrology teams. Apply advanced analytics, Artificial Intelligence, simulation, and experimental methodologies to accelerate learning, identify root causes, and improve overlay performance. Technology Development & Problem Solving Lead simulation and experimental process development activities, balancing modeling with hands-on characterization and technology development. Develop and maintain overlay error budgets, validation plans, experiments, and technical assessments that connect process behavior to device and integration requirements. Solve complex overlay challenges involving alignment, distortion, deformation, process interactions, and bonded wafers. Translate technical findings into actionable process improvements, technology decisions, and roadmap recommendations. <

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an Physical Design Engineer to lead cross-functional efforts to solve complex physical design challenges and develop end-to-end RTL-to-GDS methodologies across advanced nodes, with a strong focus on PPA and runtime improvements. The engineer will architect, integrate, and deploy AI/ML-driven solutions into production physical design flows, creating custom CAD tools and partnering with internal teams and EDA vendors to drive next-generation, ML-enabled capabilities. This role is hybrid, based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are BS in Electrical or Computer Engineering (or equivalent experience) with 5+ years in Physical Design CAD methodology at advanced nodes. Proven track record improving PPA and/or runtime on high-performance, low-power taped-out designs. Hands-on with industry-standard EDA tools (e.g., Fusion Compiler) across synthesis, P&R, STA, signoff, and hierarchical flows. Strong Python/Tcl and data skills, with interest or experience in ML frameworks (PyTorch, TensorFlow), and the ability to drive complex projects independent

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid , based out of Austin, TX, Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A hands-on engineer with deep expertise in SOC/ASIC physical design and a track record of successful tapeouts. Passionate about optimizing PPA through innovative implementation techniques and close RTL collaboration. Strong problem solver who excels at debugging complex issues across design hierarchies. Collaborative team player who thrives in fast-paced, technically challenging environments. What We Need BS/MS/PhD in EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler II. Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementati

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in STA and passionate about enabling silicon to meet aggressive performance goals. Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies. A collaborative team player who works well across logic, DFT, and physical design boundaries. Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows. What We Need 7+ years of industry experience and a proven record of successful tapeouts. Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis. Proficiency in writing and debugging SDC constraints, creating ECOs, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

At Snowflake, we are powering the era of the agentic enterprise. To usher in this new era, we seek AI-native thinkers across every function who are energized by the opportunity to reinvent how they work. You don’t just use tools; you possess an innate curiosity, treating AI as a high-trust collaborator that is core to how you solve problems and accelerate your impact. We look for low-ego individuals who thrive in dynamic and fast-moving environments and move with an experimental mindset — who rapidly test emerging capabilities to discover simpler, more powerful ways to deliver results. At Snowflake, your role isn't just to execute a function, but to help redefine the future of how work gets done. We're looking for a Director of Engineering to join our leadership team in the AI Functions product portfolio, a hybrid director/principal engineer role at the forefront of AI-powered analytics. Our mission is to democratize AI by surfacing powerful AI functions directly in SQL for analyzing structured and unstructured data, with minimal configuration. We handle the full AI lifecycle behind the scenes, so data analysts, engineers, and scientists can build data transformation pipelines with AI using the most sophisticated building blocks seamlessly within their existing SQL workflows. The AI Functions product portfolio represents one of the most strategic and impactful product surfaces within Snowflake, bringing together two of the company's core strengths: its industry-leading ability to process massive volumes of data and its growing capability to make that data AI-ready. By embedding advanced AI and LLM-powered functions directly into SQL, this portfolio transforms Snowflake from a data platform into an intelligent data system where structured and unstructured data can be seamlessly prepared, enriched, and analyzed using AI at scale. This convergence enables customers to operationalize AI within their existing workflows, unlocking faster insights, more powerful applicatio