Methodology in United States

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. In the Principal Engineer position, you will lead technical verification approaches to strengthen DRAM verification quality, standardization, and traceability throughout project families and pillars. You will invent the next generation of intelligent verification workflows and continuously advance scalable verification systems that align with new products, features, evolving design techniques (including RTL-focused flows), and scalable, family-based product development. This role is ideal for someone who excels in uncertain situations, enjoys forging new paths, and wants to impact verification across the DRAM roadmap. Responsibilities Verification Quality and Methodology Governance Define and drive DRAM verification methodology, quality standards, and AI-enabled strategies to improve coverage, traceability, efficiency, and defect prevention. Lead closed-loop silicon learning by identifying verification gaps, incorporating lessons learned into requirements and standard methodologies, and reducing recurring silicon issues. Own and continuously improve the JAMA requirements framework, ensuring alignment, scalability, and adoption across projects and teams. Simplify and optimize verification workflows through automation, AI, and process improvements that reduce cycle time and accelerate debug. Partner across engineering teams to drive methodology decisions, align collaborators, and scale verification approaches. <h2

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Summary As an MTS Design Verification Engineer, you will serve as a technical leader driving innovation in DRAM verification for advanced memory products. This role focuses on leading design and verification strategy, influencing key technical decisions, and ensuring high-quality, functionally correct, and scalable memory solutions. You will collaborate with global teams, guide methodology improvements, mentor engineers, and act as a domain expert to support next-generation DRAM technologies. Responsibilities Lead DRAM verification innovation, driving key technical decisions, architecture, and strategy during product execution Collaborate with global teams to define and implement best-known methods for verification and product development Drive verification planning, coverage closure, and silicon debugging for advanced DRAM products Evaluate and implement new tools, methodologies, and flows to improve verification efficiency and quality Mentor engineers and provide technical leadership while contributing expert guidance to senior leadership teams Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field 8&#43; years of experience in DRAM/memory or advanced CMOS verification Strong circuit analysis and debug skills at the transistor level — able to root-cause behavior, not only at the testbench level Experience with simulation tools such as HSPICE, Finesim, Verilog, or SystemVe

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s High‑Bandwidth Memory (HBM) Digital Design organization is seeking a Digital Physical Design Engineer to drive backend implementation of high‑performance, low‑power digital logic used in advanced memory products. This role spans backend implementation from Netlist to GDSII, with a strong focus on timing closure, power integrity, and manufacturability in advanced process technologies. The successful candidate will work closely with RTL, DFT, CAD, and verification teams to deliver high‑quality physical designs, contribute to methodology improvements, and help push performance, power, and area (PPA) targets in complex, multi‑hierarchy designs. Key Responsibilities: Own and execute physical design implementation from synthesized netlist through GDSII, including floorplanning, placement, clock tree synthesis, routing, and physical signoff Utilize AI-Enabled tools in the Netlist to GDS flow Perform and drive timing closure across multiple modes, corners, and scenarios using industry‑standard STA tools Analyze and resolve congestion, timing, IR drop, EM, and power integrity issues Develop and refine floorplans, power grids, and clocking strategies for high‑performance designs Work with placement and timing closure of custom analog hard IP macros in a digital-on-top design flow Collaborate closely with RTL designers to influence partitioning, constraints, and micro‑architecture decisions early in the design cycle Implement and va

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Welcome to Micron’s Advanced Mask Development Group! We are a group of engineers who provide advanced technology solution of Optical Proximity Correction (OPC) and Resolution Enhancement Techniques (RET) to support wafer process development. Through the rigorous simulation and data analysis, we develop the optimization strategy and methodology in reticle design to support all Micron products, using various tools, scripts and programming to improve process window of semiconductor process on wafers. You will have the opportunity to participate and to collaborate in a group project, together with an experienced RET engineer, to work on the intersection of AI agents and advanced OPC / RET techniques to help automate part of the RET development flow. Responsibilities: Study and comprehend photolithography modeling theory and simulation methodology. Build AI work flow and programs for RET/OPC tasks. Improve beyond the existing metrics achieved by the Process-Of-Record. Build a document of Best Known Method based from your learning, and to detail the thought process and the supporting data. Work on a hands-on and collaborative project with the Photolithography group in Technology Development. Build automated scripts and/or program to improve the efficiency of the current methodology. Identify potential opportunities of improvement, including areas which can be challenging to achieve during the internship period. </l

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions for AI, machine learning, and high-performance computing applications. We are seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. This role focuses on PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks that enable industry-leading bandwidth, power efficiency, and robustness. The successful candidate will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture teams to define architectural requirements, drive technology innovation, and ensure successful translation from concept to silicon. As a technical leader, you will influence future HBM roadmap decisions, develop engineering methodologies, and mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design. Key Responsibilities Define and drive next-generation HBM PHY and IO architecture , balancing performance, power, area, reliability, and manufacturability requirements. Architect high-performance transmit and receive paths , including clocking, signaling, equalization, timing alignment, and interface optimization. Define and optimize analog calibration architectures , including impedance calibration, reference v

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsible for starting up, developing and optimizing processes to improve product quality and reliability, working on process yield improvement, cost reduction, productivity improvement and risk management as well as resolving manufacturing line problems. Identify, diagnose and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. Handle new process baseline qualifications and managing. Identify, diagnose and resolve assembly process related problems. Coordinate and execute process, equipment and material evaluation and optimization initiatives and implement changes at process step. Lead and participate in continuous yield improvement and cost reduction activities. Validate and fan out new process baseline qualified, including new processes, tools and materials for new product introduction. Support site to site portability. Manage and audit material suppliers to achieve quality, cost and risk management objectives. Support internal and external audits. Develop new or modified process formulations, define processing or handle equipment requirements and specifications, and review processing techniques and methods applied in the manufacture, fabrication, and evaluation of products. Coordinate design requirement review with appropriate engineering/scientific personnel to ensure compatibility of processing methods. Compile and evaluate test data to determine appropriate limits and variables for process or material specifications. Plan projects involving definition and selection of new concepts, equipment automati

The Senior Enterprise Applications Analyst, Procurement supports the evolution, implementation, and integrity of TaylorMade's Oracle ERP solutions across global procurement and supply chain operations. This role provides functional expertise and day-to-day operational support for Procure-to-Pay (P2P) processes, while partnering with business stakeholders to drive measurable process improvement and align system capabilities with strategic objectives. The analyst supports enterprise initiatives including system upgrades, automation, and cloud migration planning. Essential Functions and Key Responsibilities: Provide day-to-day functional support for Oracle Procurement, including troubleshooting issues and ensuring uninterrupted requisitioning, purchasing, and supplier management operations. Configure and maintain Oracle Procurement setups, including organizational structures, Approval Management Engine (AME), document types, supplier configurations, item and category hierarchies, iProcurement, and profile options. Gather, analyze, and document business requirements using Oracle AIM methodology, and translate them into detailed functional specifications for development. Evaluate existing business processes, identify gaps and improvement opportunities, and recommend Oracle standard solutions that deliver measurable business value, including cost savings, efficiency improvements, and return on investment (ROI). Develop, coordinate, and execute functional, system integration (SIT), user acceptance (UAT), and regression testing activities; perform root cause analysis and resolution of production issues. Support and troubleshoot integrations between Oracl

Where Performance Meets Purpose Join a team that values excellence and innovation, at a company known for its iconic golf brands. At Acushnet Company, your background and experience contribute to creating the best products for dedicated golfers worldwide. Here, your performance has purpose. What You Will Be Doing We’re seeking a highly organized and results-driven Lead ERP Program Manager to lead critical business transformation initiatives as part of Acushnet’s global SAP S/4HANA transformation program. In this role, you will be responsible for the successful planning, governance, execution, and delivery of complex ERP programs, application development initiatives, and enterprise-wide business transformation efforts that support strategic organizational objectives. You will partner closely with business leaders, SAP functional and technical teams, project stakeholders, and external implementation partners to ensure projects are delivered on schedule, within budget, and aligned with business priorities. Serving as a key leader within the program organization, you will establish governance structures, manage project plans and dependencies, oversee resource allocation, and proactively identify and mitigate risks to drive successful outcomes across multiple workstreams. You will lead the execution of global SAP S/4HANA initiatives, including greenfield implementations, major system enhancements, application development efforts, and process modernization programs. Throughout the project lifecycle, you will oversee all phases from discovery and design through implementation, hypercare, and sustainment while ensuring adherence to SAP Activate methodology, Agile practices, and established program management standards. The role will require

Where Performance Meets Purpose Join a team that values excellence and innovation, at a company known for its iconic golf brands. At Acushnet Company, your background and experience contribute to creating the best products for dedicated golfers worldwide. Here, your performance has purpose. What You Will Be Doing Are you passionate about delivering exceptional service and building lasting relationships? Join us as an Account Representative, where you’ll be the trusted voice for our Trade Accounts—guiding them through product options, order management, and program support. In this fast-paced, collaborative role, you’ll provide critical inside support to our Field Sales team, manage custom and stock club orders, and offer expert insights on product features and availability. You’ll also play a key role in solving challenges, identifying trends, and contributing to exciting initiatives across the organization. Bring your energy, expertise, and customer-first mindset to a team that’s committed to excellence and innovation in every interaction. What You Bring Bachelor’s degree preferred; 2&#43; years of golf or customer service experience accepted in lieu 2–4 years of customer service or golf industry experience required (or 1&#43; year as an Acushnet CSR) Strong computer proficiency and ability to manage multiple systems Familiarity with Titleist SureFit fitting methodology and premium golf retail strongly preferred Excellent time management, organization, and multitasking skills Ability to sit and work at a PC for extended periods; must be able to lift/carry golf club bags for events Must maintain confidentiality around pricing, programs, and ac

Why Sony Interactive Entertainment? Sony Interactive Entertainment isn’t just the Best Place to Play — it’s also the Best Place to Work. Sony Interactive Entertainment (SIE) is the company behind the PlayStation brand. As a subsidiary of Sony Group Corporation, we’re part of a proud legacy of innovation and excellence. SIE is a dynamic technology company, delivering cutting-edge hardware and network services to more than 100 million people and an entertainment leader, home to some of the most beloved and recognizable intellectual properties (IP) in the world. Our role at SIE is to create and nurture the experiences under the PlayStation brand, a name synonymous with entertainment excellence and creativity. Are you a curiosity driven technologist who can quickly understand how an AI system works, identify where it could be misused or fail, and help a team find a practical path forward? Sony Interactive Entertainment is seeking a Senior AI Security Risk Analyst to provide hands-on security support for AI systems, agents, workflows, tools, and integrations across SIE. Role Summary: In this role, you will operate at the intersection of modern AI technology, security risk, architecture, and enablement. You will conduct AI security reviews using SIE’s established security risk assessment methodology, policies, standards, and control expectations, adapting their application to AI-enabled and agentic systems and identifying where AI-specific guidance or controls are needed. You will coordinate risk-focused design and architecture input and translate AI-specific weaknesses into decision-ready recommendations and engineering actions. You will serve as an approachable security partner, working cross-functionally with teams across SIE’s business units and functions to support a diverse range of AI use cases, systems, and technologies. You will work especially closely with Responsible AI & Governance and coordinate expertise across Information Security teams and IT &amp

This is where your work makes a difference. At Baxter, we believe every person—regardless of who they are or where they are from—deserves a chance to live a healthy life. It was our founding belief in 1931 and continues to be our guiding principle. We are redefining healthcare delivery to make a greater impact today, tomorrow, and beyond. Our Baxter colleagues are united by our Mission to Save and Sustain Lives. Together, our community is driven by a culture of courage, trust, and collaboration. Every individual is empowered to take ownership and make a meaningful impact. We strive for efficient and effective operations, and we hold each other accountable for delivering exceptional results. Here, you will find more than just a job—you will find purpose and pride. Your Role at Baxter This role involves collaborating with clinicians, engineers, and cross-functional partners to improve usability, safety, and efficiency for hospital beds, mobile and overhead patient lift systems, and other product portfolios. Your efforts will directly support developing new products and sustaining engineering initiatives. When you come on board at Baxter as a Principal Engineer, Human Factors, you will apply your analytical methodology to pinpoint risks and opportunities for innovation promptly. Nimble and ready to act, you maintain composure in high-pressure situations. What you'll be doing Lead and drive implementation of training, continuous improvement efforts, and overall initiatives to improve functional outcomes. Conduct user research, usability testing, and user-centered development activities to ensure our products meet customers' needs and mitigate risk effectively. Develop and maintain human fact

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Department Intro: The Advanced Packaging Technology Development (APTD) department at Micron Technology is at the forefront of innovation, driving the advancement of memory and storage Interconnects and Packaging solutions that transform how the world uses information. Our team is dedicated to developing innovative processes and technologies that enable the creation of next-generation semiconductor products which drive the AI revolution. Position Overview: As a Staff Process Engineer in Advanced Packaging CMP team, you will be primarily responsible for starting up, developing and optimizing processes to improve product quality and reliability, working on process yield improvement, cost reduction, productivity improvement and risk management as well as resolving manufacturing line problems. You will also be required to identify, diagnose and resolve assembly process related problems by applying failure analysis, FMEA, 8D or SPC/FDC methodology. This position requires communication and collaboration with associates both within the region and internationally. Strict adherence to Micron Intellectual Property Protection policy is vital. This role will also extensively collaborate with vendors to develop processes that meet integration requirements. Responsibilities: Perform fundamental research, consumables development, and hardware evaluation, as well as test processes for novel applications Initiate and manage experiments to widen process margins and evaluate man

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are a world - class autonomous driving hardware and software development team. We have the best platform and have maintained a leading position in the field of artificial intelligence. Next, we will continue to deepen our efforts in the autonomous driving field and strive to bring sustained growth to our customers. We're looking for a Senior Software Triage Engineer with strong technical ability to deeply understand architectures and strong scripting experience to automate and Triage methodology, and the leadership to encourage our engineering team. As a key member of our automotive group, you'll be working on the real time challenges outstanding to the automotive industry and our automotive products. This is a key role to support AV software agile iteration & development for the release of clients, together working with the engineering teams, understanding the AV stack deeply and providing data-based judgement and delivering high-quality AV software to end customer. What you’ll be doing: Work with Product, Engineering, Model/SW Devs, In-car testing, Fleet teams on test request and triage planning, do live triage with accurate analysis and debugging steps, present top issues by end of day. Deep understand

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5&#43; years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of