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Treasury is leading a Finance wide capability for an AI-augmented operational model and process for variance analysis; this role will support the execution of that effort, providing key domain expertise and execution support. Day-to-day, the candidate will act as a key business contributor for the OM / AI capability build, supporting the delivery of the variance analysis process — including a prototype to be leveraged across Finance. This includes assisting in the definition of use case requirements, validating outputs, and helping to ensure the resulting tooling is fit for finance-wide reuse. The output of this work will contribute to establishing the reusable OM / AI pattern that subsequent Finance teams will adopt. This role requires an understanding of OM and AI strategic direction of the Finance function, combined with a solid conceptual/practical grounding in Liquidity Operations process. Excellent communication and collaboration skills are required in order to work effectively with internal stakeholders across various levels. Impact reflects professional influence on the business and close interaction with other functions and businesses. Responsibilities • Support the development and implementation of AI tooling to help establish a Finance wide common capability for variance analysis, including daily and periodic identification, root-cause analysis, and escalation of material variances across product, entity, and currency dimensions. • Collaborate within Treasury, across Finance, and with Technology to identify consistent attribution of variance drivers — including intra-day movements, and operational breaks. • Assist in preparing and presenting executive-level commentary and analysis to senior management on progress. • Contribute to the operating model process including supporting the documentation of escalation paths and process flows. Qualifications • 10+ years of experien

Work Flexibility: Hybrid or Onsite Stryker is hiring a Senior Quality Engineer to join our Neurovascular division. This is a hybrid r ole based in Fremont, CA or Salt Lake City, UT . As the Senior Design Quality Engineer , you will be actively involved in Product Risk Management, Post Market Surveillance, Design Control and Product Quality Improvement. You will be involved in a fast-paced mix of short design change efforts and will be responsible for product risk management and adherence to design control requirements throughout the product lifecycle. You will be responsible for ensuring that post market data and feedback is channeled into the risk management system throughout the product lifecycle. You will make regular use of problem-solving tools and statistical analysis to analyze and trend data and provide quality input into technical investigations, perform test method development and validation, design verification, risk assessment and design reviews. You will be responsible for supporting product testing and failure analysis, writing protocols and reports, creating and maintaining risk files and assessing the impact of necessary changes to our products. You will lead initiatives to increase sales and improve the customer experience of our devices. Neurovascular (NV) products push the boundaries of technology to meet ever increasing product performance requirements, making the goal of assessing and demonstrating, safety, performance and compliance an exciting challenge. What You Will Do Develop qualification plans, protocols, and reports for new products, existing products, components, and subassemblies. Execute product testing, inspection, verification, and validation activities to support design and quality objectives. Perform failure investigations and root cause anal

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity We are seeking a system validation engineering intern to help drive server blade and rack validation efforts for next-generation AI infrastructure hardware systems. This role focuses on post-silicon system validation across the full lifecycle of server hardware systems, ensuring functional and performance meets product objectives. You will help drive end-to-end blade and rack validation including development, execution, and debug while collaborating across silicon, firmware, systems, and platform teams. The Blade and Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Help drive and execute post-silicon validation goals of AI compute blades and racks including testcase planning, development, and automation Help drive validation testcase execution and system debug against program achievements and report validation progress and risks. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness Triage test failures, collect debug data, and collaborate on root cause analysis. Track validation coverage and continuously improve test processes and infrastructure. What You’ll Bring Working towards a Bachelor's

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that provide the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing transformative technologies. Our AI Engineering Campus in Austin plays an important role in building the hardware platforms that support the next generation of AI systems. The Opportunity We are looking for a recent graduate or early-career engineer to join the Mech/Thermal Platform team as a Graduate Mechanical Engineer. You will contribute to the mechanical design, thermal validation, and verification of advanced AI hardware and data center systems. You will work with experienced mechanical, thermal, hardware, and systems engineers throughout the development lifecycle. The role combines 3D computer-aided design, prototype evaluation, lab testing, data analysis, troubleshooting, and clear engineering documentation. What You Will Do Create and update mechanical parts, assemblies, and drawings using Creo or comparable 3D CAD software. Take ownership of defined mechanical design tasks from requirements and concepts through detailed design, review, release, and verification. Apply mechanical design, materials, manufacturing, heat transfer, and thermodynamics principles to engineering decisions. Develop mechanical and thermal test plans and procedures for prototypes and development systems. Set up and operate laboratory equipment, collect accurate data, analyze results, and document conclusions. Evaluate prototypes and identify mechanical, thermal, assembly, or manufacturability issues. Support design verification, troubleshooting, root-cause analysis, and implementation of verified design improvements. Maintain accurate engineering documentation, including design notes, drawings, test procedures, results, and change r

Job Details: Job Description: The Thin Films Senior Process Engineer will support PVD, CVD, and ALD technologies for dielectric and metal thin-film deposition in a high-volume manufacturing environment. Key Responsibilities Apply advanced expertise in thin-film deposition processes to drive continuous improvement in process performance, sustainment, and technology development. Collaborate with upstream and downstream partners to deliver manufacturing improvements through strong cross-functional engagement and stakeholder management. Own manufacturing processes and/or equipment, ensuring achievement of key performance indicators (KPIs) including safety, quality, cost, productivity, defect reduction, and yield improvement. Develop and execute strategic plans for complex projects, coordinating timelines and dependencies across multiple teams and initiatives. Support manufacturing capacity expansion and technology transfer activities to enable successful ramp-to-volume production. Partner with equipment vendors and cross-functional stakeholders to troubleshoot technical challenges, improve tool performance, and enhance operational efficiency. Lead process development initiatives that support current and next-generation high-volume manufacturing technologies. Design and optimize excursion prevention and detection systems to strengthen process control and minimize manufacturing risk. Lead equipment installation, conversion, qualification, and readiness activities during factory ramps, ensuring all tools are deployed safely, on schedule, and in compliance with quality and manufacturing standards. Drive root cause analysis and implement corrective actions to resolve process and equipment-related issues while improving overall manufacturing stability and performance. <p st

We’re building a world of health around every individual — shaping a more connected, convenient and compassionate health experience. At CVS Health®, you’ll be surrounded by passionate colleagues who care deeply, innovate with purpose, hold ourselves accountable and prioritize safety and quality in everything we do. Join us and be part of something bigger – helping to simplify health care one person, one family and one community at a time. Position Summary At Aetna®, part of CVS Health, we proudly serve more than 26 million medical members through our broad range of health plan offerings. We're committed to delivering a simpler, more meaningful, and personal health care experience to each of them. As a Senior Manager Medicare Product, Vendor Management Contract Lead you will play a critical role contracting, negotiations, oversight of vendors and assisting in achieving CVS goals, work strategically together, and remain as adaptable as possible in an ever-changing environment. This role's scope of responsibility includes overseeing the following in relation to Medicare Product vendor management: Finance, Contracts, Invoicing, Negotiations, Provisioning, Aetna Medicare Supplemental & Duals benefits, Vendor relationship management, Compliance oversight, Auditing, and projects as assigned. The Senior Manager, Vendor Management Contract Lead is a high impact role. You will lead advance contract and negotiation skills, work with other partner to identify root cause, address, and resolve vendor issues, manage vendors to the contract SLAs, performance guarantees and provide insight into complex vendor problems. Responsibilities include: Work assignments involving moderately complex to complex issues where the analysis of situations or data requires an in-dep

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron’s DRAM Product Architecture Group partners across fabs, test, module, and system teams worldwide to deliver high-performance memory products. We work across geographies and functions to solve complex technical challenges, drive product innovation, and enable industry-leading DRAM solutions. Our team values collaboration, continuous learning, and making a measurable impact through engineering excellence. As a New College Graduate DRAM Yield & Quality Engineer, you will play a key role in monitoring and improving the health of Micron’s server DRAM products. Working with experienced engineers and cross-functional teams around the globe, you will analyze product and manufacturing data, investigate technical issues, and contribute to strategies that improve yield, quality, and performance throughout the product lifecycle. This is a highly visible role with direct impact on customer success and product reliability. Responsibilities Analyze silicon parametric, test, and manufacturing data to identify trends, resolve product issues, and support root cause investigations. Contribute to yield and quality improvement initiatives across new product introduction (NPI), qualification, ramp, and high-volume manufacturing. Collaborate with fab, test, module, quality, and operations teams to drive execution of product health objectives. Develop and maintain automation solutions to improve engineering efficiency, data analysis, and reporting. Apply AI, Agentic AI, and Generative AI tools to en

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsible for understanding the processes used to assess and mitigate risks related to the introduction of new package technologies so that you can improve efficiency and effectiveness by implementing automation, data analysis and machine learning/AI solutions. Set up data bases, develop data ingestion pipelines, and implement automated data analysis and reporting tools. Support problem solving and risk assessment for internal or customer quality issue by pulling and analyzing data. Contribute to the advancement of technology at Micron through mentoring, publishing technical papers (internal and external), and developing innovative solutions to challenging problems. Implement Automation, Data Analysis, and AI Solutions. Collaborate with Engineering teams to Map Package DDQA processes and data streams. Set up and optimize databases and develop solutions to improve efficiency and effectiveness. Understand the needs of internal customers and develop solutions. Support Problem Solving and Risk Assessment for Quality Issues. Pull relevant product information, manufacturing data, and reliability data based on given problem statements. Determine the appropriate dataset and treatment required to answer questions posed by problem solving teams. This could include producing data visualizations, machine learning models, statistical inferences, and web applications. Provide recommendations about root cause findings and product risk, based on data analysis. Collaboratively Communicate Findings and Best Practices. Share best practices with global teams to enable a cultur

Experienced Electrical & Test Engineer Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks an Experienced Electrical and Test Engineer to serve as an Automated Test Equipment Engineer to join our Patriot Advanced Capability-3 (PAC-3) Electrical Engineering Capability Team in Huntsville, AL . We design, sustain, and upgrade next generation electronics concepts and support production and special test equipment design for increasing capacity requirements. Position Responsibilities: Support design of automated test equipment, development of engineering documentation, and hardware fabrication, integration, and validation testing Develop, document, and maintain electronic and electrical system requirements according to customer desires and contract requirements Create and implement overall Test Equipment Design strategies Review and apply real-time test anomaly troubleshooting and resolution of issues encountered during hardware validation and verification testing Support fielded test equipment hardware and software over the entire product lifecycle Research emerging technologies for potential applications to meet projected requirements Perform Root Cause Corrective Action (RCCA) investigations, troubleshooting, and resolutions This position requires the ability to get a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Sc

Firmware Engineer BIOS/UEFI Description - The Firmware Engineer is responsible for ensuring that embedded firmware meets the highest standards of quality, robustness, and long‑term reliability. This role works closely with firmware developers, hardware engineers, architecture teams, QA, and cross‑functional partners to define quality metrics, validate system behavior, improve defect detection, and build processes that prevent regressions. Responsibilities Develop, execute, and maintain comprehensive firmware test plans, including functional, regression, stress, corner-case, and long-duration reliability tests. • • • Evaluates the firmware architecture, design and development plus testing methodologies to create strategy and implement methods to bring increased quality and reliability to the firmware. Reviews firmware code and test plans including functional, regression, stress, corner-case and long-duration reliability tests. Perform root-cause analysis for firmware defects, drive containment, corrective actions, and verification of fixes. Create and manage quality dashboards, KPI, failure rates, and reliability metrics. Evaluate failure modes exposed during design, development, manufacturing and field use; propose design or process improvements to prevent recurrence. Works with product architects, firmware teams, product managers and provides critical guidance, system-level debugging and troubleshooting to various teams, as a Subject Matter Expert. Reviews and evaluates designs and project activities for compliance with systems design and development guidelines and standards; provides tangible feedback to improve product quality and mitigate failure risk. Create and manage quality dashboards , KPIs, failure rates, and reliability metrics. Validate firmware integration with hardware, BIOS/UEFI, EC, micro

Become a part of our caring community The Actuarial Analyst 2, Analytics/Forecasting analyzes and forecasts financial data to provide accurate and timely information for strategic and operational decisions. Establishes metrics, provides data analyses, and works directly to support business intelligence. Your work assignments are varied and frequently require interpretation and independent determination of the appropriate courses of action. The Actuarial Analyst 2, Analytics/Forecasting will report to the Actuary, Analytics/Forecasting. You will play a key role in the Medicare actuarial forecasting process. This position entails the maintenance of the provider revenue and expense projection model and associated tools supporting the projection model. The Actuarial Analyst 2, will be responsible for integrating value-based provider impacts into financial and bid forecasts, managing tools associated with these impacts, and providing guidance on effective risk modeling practices. The Actuarial Analyst 2, Analytics/Forecasting ensures data integrity by developing and executing necessary processes and controls around the flow of data. You will collaborate with stakeholders to understand business needs/issues, troubleshoots problems, conduct root cause analysis, and develop cost effective resolutions for data anomalies. You will understand department, segment, and organizational strategy and operating objectives, including their linkages to related areas. You will make decisions regarding own work methods, occasionally in ambiguous situations, and require minimal direction and receives guidance where needed. You will follow established guidelines/procedures. Use your skills to make an impact Required Qualifications Bachelor's Degree Successful completion of at least 3 actuarial exams<

The Silicon Co-Design Group (SCG) sits at the crossroads of architecture, design, marketing, operations, and productization. Our work spans early architecture through final product delivery across Datacenter, Gaming, Robotics, Automotive, and Embedded markets. We work closely across functions to deliver chips that change what is possible. NVIDIA’s Silicon Co-Design Group is hiring a Chip Lead to serve as the technical lead for one of our most consequential silicon programs! This is not project management, and it is not a senior IC role. You are the person the program partners with on its hardest technical questions — when the right answer is not obvious, and when leadership needs a single technical perspective to align on direction. You are accountable for the technical integrity of the chip end-to-end. You guide co-design feature integration, help resolve the toughest multi-functional bugs, and serve as the project-specific custodian of the qualification playbook. The program runs cleaner because you are on it! What you’ll be doing: You will partner across design, validation, software, and manufacturing to keep the program’s technical narrative clear and on track. Day to day, you will: Serve as the single technical point of contact for multi-functional decisions, issues, and trade-offs. Co-lead program-level feature integration from chip to system, surfacing inter-function dependencies and guiding them to resolution. Help resolve the program’s hardest multi-functional bugs by translating ambiguous, multi-team symptoms into root-cause closure on areas such as HBM, power and thermal, high-speed I/O, and packaging. Steward the qualification playbook. When the playbook does not fit a situation, guide the mitigations and capture the lessons as reusable methodology for other SSG programs. Shape the program’s technical narrative by surfacing key risks, trade

NVIDIA’s Silicon Co-Design Group is the team that gets every GPU, SoC, and CPU silicon program from first power-on to high-volume production. We are hiring a Senior Manager to lead our Test, Manufacturability, Reliability & Quality (TMRQ) organization. This is not a coordination role . Your work decides if a product can be built at scale and trusted in the field. These include production test development (SLT, BLT), control run flow, system reliability stress (HTOL), platform- and board-level manufacturing issue closure, and field diagnostic test development. You lead a team of individual contributors and a first-line manager at the layer where silicon, platform, and software collide with manufacturing reality. Decisions you make show up in yield curves, production ramp , and customer escapes. You are the leader the program turns to when a build is stuck, a control run is fallout-heavy, or a field return points back at silicon . The exceptional hire also uses AI deliberately — with demonstrated workflow impact and the judgment to know where it compresses real work and where it introduces risk. What you will be doing: Keep programs moving. Own the technical execution and velocity of SLT, BLT, Board/Chip/Rack CR, and system reliability stress (HTOL) across every GPU, SoC, and CPU silicon program. Close the hardest multi-functional failures. Resolve Vmin and binning escapes, performance shortfalls, and power anomalies by driving root-cause across design, methodology, DFT, ATE, package, software/firmware, and manufacturing — and own the WARs and productized fixes through to confirmation. Give leadership the clarity to act. Convert raw integration signals — CR fallout, BLT/SLT yield, SHTOL/CHTOL data, RMA trends, customer escalations — into decision-ready options that enable executive leadership to act with confidence on POR, QS/PS gates, a

NVIDIA's accelerated computing platforms move data at speeds that push the limits of what silicon and physics allow. Whether a high-speed interface trains reliably, maintains accurate margins, and survives every platform topology it will ever see is a question we answer ourselves. This role does that work. The Silicon Co-Design Group leads the boundary between what was designed and what was built. When a GPU, CPU, or SoC ships with interfaces that work at scale, this team is the reason. Most engineers debug within a layer. You will own the full stack. When an interface fails to train, the link margin is unexpectedly tight, or a customer reports a critical silicon issue, you trace the problem through protocol behavior, signal integrity, firmware, platform topology, and silicon marginalities. You then confirm that the fix works. Your methodology shapes how NVIDIA validates high-speed interfaces across generations. Your decisions affect yield, production ramp, and field quality. This is not a coordination role. The engineers who do it well hold protocol depth and system breadth simultaneously, never lose the thread across hardware, firmware, and software, and have the judgment to know when to go deeper and when to act. They are rare. Should that describe you, read on. What you'll be doing: Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness. Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation. Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria f

NVIDIA has been redefining computer graphics, desktop gaming, and enhanced computing capabilities for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As a NVIDIAN, you will work on problems that sit at the boundary of architecture, silicon, firmware, software, and production, where strong judgment matters as much as technical depth. We're the Silicon Design for Productization (DFP) Team, within the broader Silicon Co-Design Group, and we turn power and thermal design into executable productization methodology. Power and thermal are among the most complicated problems we work on at NVIDIA because they sit at the intersection of architecture, workload behavior, silicon variation, firmware policy, platform constraints, and product goals. Small decisions here have an outsized impact on performance, efficiency, reliability, bring-up speed, and ultimately what the product can deliver in the field. We define how features move from concepts to bring-up, characterization, validation, and release. In this role, you will help us build that bridge. We're looking for an engineer who reasons from first principles, flourishes with ownership in a fast-paced environment, and uses AI with sound judgment. What you’ll be doing: Lead the effort across multi-functional teams to keep the program’s power and thermal productization strategy clear, executable, and on track. Create methodology and silicon test plan based controller designs and architecture, including characterization process, debug tools, fuse/firmware settings and lab requirements. Drive resolution for challenging silicon issues through structured hypotheses, measurement plans, and root-cause closure. Steward the Power and Thermal playbook when the existing productization methodology