Senior Design Manager in United States

Senior Human Centered Design Researcher — Mounds View, Minnesota, United States of America. Apply via Workday.

Experienced or Senior Digital CCA Design Company: The Boeing Company Boeing Defense, Space & Security (BDS) seeks a Digital CCA Design Engineer who is a subject matter expert in high-speed digital circuit design , signal integrity analysis , and electrical design to join our time in Huntsville, AL. This position will p lay a vital role in the Patriot Advanced Capability-3 (PAC-3) program, one of the world's most advanced air and missile defense systems. This is your opportunity to work in a dynamic environment where your skills will directly contribute to protecting critical assets and ensuring mission success. If you are passionate about defense technology and want to make a real impact, we want to hear from you! Position Responsibilities: Focus on electrical design, simulation, verification, and validation testing of high-speed printed circuit board design and electronic system Lead product development cycles Collaborate with cross-functional teams, including other engineering disciplines Keeping current on related industry best practices and technological advancements This position requires obtaining a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim U.S. secret clearance Pre Start and final U.S. secret clearance Post Start is required. Basic Qualifications (Required Skills/Experience): Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement. 3 or more years of related experien

Electronic System Design and Analysis Engineer (Experienced or Senior) Company: The Boeing Company The Boeing Test Operations and Engineering (TO&E) team in Berkeley , Missouri is seeking an Electronic System Design and Analysis Engineer to join our Instrumentation Installation Design group to support all major programs in the St. Louis area. We are currently hiring for a broad range of experience levels including Experienced and Senior Electronic System Design and Analysis Engineers. Position Responsibilities: Electrical Design & Testing AC and DC power applications Assisting shop with build information Reading electrical drawings/schematics Troubleshooting Electrical component/wiring faults Production Functional and Environmental Acceptance Testing Designing new test sets for various weapon and aircraft electronics Performs system tests to verify operational and functional requirements Supports resolution of product integration issues and production anomalies Researches basic technologies for potential application to company business needs Assists in monitoring suppliers' performance to ensure compliance with requirements Develops or modifies basic hardware and software designs based on defined requirements Assists with the development and documentation of electronic and electrical system requirements This position is expected to be 100% onsite. The selected candidate will be required to work onsite at one of the listed location options. Basic Qualifications (Required Skill/Experience): <

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer who will contribute to the physical design of high-performance chips for industry-leading AI/ML architectures, spanning implementation from synthesis through tapeout. You will partner with front-end and physical design engineers to optimize floorplanning, timing, power, performance, and area across multiple IPs. Along the way, you will build end-to-end ASIC expertise while learning from experienced engineers across the chip development process. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are An engineer excited to work on high-performance designs for industry-leading AI/ML architectures. A collaborative problem solver who enjoys working with experienced engineers across ASIC disciplines. Grounded in logic design fundamentals and gate- and transistor-level implementation. Curious about how early architectural and RTL decisions shape physical implementation and final chip quality. What We Need A BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a relat

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff. Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners. A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams. What We Need Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results. Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking an exceptional Senior-level Physical Design Engineer to drive top-level implementation of our complex AI and CPU System-on-Chip designs. You'll orchestrate cross-disciplinary collaboration, implementing sophisticated floorplans, power grids, and clock networks while ensuring design closure at the chip level. If you excel at managing the complexity of full-chip physical design and want to deliver next-generation AI hardware, we need your expertise. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. Passionate about optimizing chip-level implementations for power, performance, and area. Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. What We Need 8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Deep expertise in hierarchic

About the Team Our Robotics team is focused on unlocking general-purpose robotics and pushing towards AGI-level intelligence in dynamic, real-world settings. Working across the entire model stack, we integrate cutting-edge hardware and software to explore a broad range of robotic form factors. We strive to seamlessly blend high-level AI capabilities with the constraints of physical systems to improve peoples’ lives. About the Role We are seeking a senior Actuator Electromagnetic Design Engineer to lead the development of custom electromechanical actuators for advanced robotic systems. You will own actuator development from early architecture and concept generation through prototype validation and system integration, partnering closely with mechanical, electrical, controls, firmware, reliability, and manufacturing teams. This role focuses on the design, integration, and validation of precision electromechanical systems, including motors, transmissions, sensing, structural components, and thermal architectures. You will help drive actuator development across the full engineering lifecycle while establishing scalable design, test, and integration practices for future robotic platforms. This role is based in San Francisco, CA, and requires in-person presence 4 days a week. In this role, you will: Lead the architecture, design, and integration of custom robotic actuators, including the design, simulation, integration and sourcing of custom electromagnetic components. Define actuator requirements and system-level trade studies around torque density, bandwidth, efficiency, thermal performance, inertia, reliability, manufacturability, and cost. Design precision electromechanical assemblies with strong attention to tolerances, alignment, load paths, thermal expansion, sealing, wear, and serviceability. Drive actuator integration into robotic systems, partnering closely with controls, firmware, electrical, and robotics software teams to optimize closed-loop performance. Devel

Datadog is entering a new chapter in how our product looks, feels, and operates. Our Design Lab is defining a new visual direction for the platform, and we’re looking for a Senior Staff Visual Product Designer to help turn that direction into a coherent product experience. Datadog is dense, technical, and used by people working through complex problems—often under real pressure. The challenge is not simply applying a new aesthetic. It is rethinking hierarchy, layout, navigation, interaction, and product patterns so the experience becomes clearer, more cohesive, and more expressive without losing the power our users rely on. This is a hands-on product design leadership role for someone who combines strong visual judgment with deep product and systems thinking. You’ll work alongside visual designers, motion designers, product designers, Design Systems, and Engineering to ensure the new direction changes how Datadog works—not just how it looks. What You'll Do Co-develop Datadog’s next visual direction by applying and stress-testing it across representative product journeys. Translate visual principles into concrete decisions about hierarchy, layout, navigation, information architecture, interaction, and behavior. Use visual language to clarify complex, data-dense experiences — hierarchy, density, and attention. Hold the visual quality bar across work you don't own, and align teams around it. Prototype, test, and refine new patterns before they become systemized. Partner deeply with Product Design, Design Systems, and engineering to turn successful concepts into durable system guidance and implementation. Create clear artifacts, pilots, and narratives that help teams adopt the direction and raise the product quality bar. Influence stakeholders across design, engineering, product, and executive partners. You will report directly to the Design Director and work as part of a small, focused team defining the future state before it scales across hundreds

Datadog is entering a new chapter in how our product looks, feels and operates. We're building a small, high-leverage Design Lab team to define that evolution, and we're looking for a Senior Staff Visual Designer to author it. Our design system powers everything we ship. Now we're ready to evolve it. As Datadog expands into AI-driven experiences and more complex product surfaces, the visual language needs to grow with it. This is the role that decides what that language is — someone with taste, judgment, and the confidence to set a direction and defend it. At Datadog, we place value in our office culture - the relationships and collaboration it builds and the creativity it brings to the table. We operate as a hybrid workplace to ensure our Datadogs can create a work-life harmony that best fits them. What You'll Do Define and evolve Datadog’s visual language across product surfaces. Lead exploratory and concept work, creating a range of distinct visual directions for the next generation of the product. Synthesize product context, research, references, and stakeholder input into clear visual principles and a coherent point of view. Establish the quality bar for typography, color, composition, iconography, imagery, motion, and visual expression across the platform. Create high-fidelity product exemplars and prototypes that make an emerging direction tangible. Partner deeply with Brand, Product Design, Motion, and Design Systems to test and refine the direction across different surfaces. Influence executives and senior stakeholders through clear, persuasive visual storytelling. Guide and critique the work of other designers, helping the visual direction remain coherent as it evolves. Help shape how visual exploration, critique, and craft are integrated into Datadog’s design process. You will report directly to the Design Director and work as part of a small, focused team defining the future state before it scales across hundreds of designers and engineers. Who Yo

The SCG Architecture team is hiring a Senior Power Integrity Co-Design Engineer to architect and deliver di/dt mitigation across silicon, package, board, and platform. This role bridges architecture, silicon, and platform — translating product noise targets into shipped specifications, and feeding silicon findings back into the next generation's build. Success in this role requires strong systems thinking and a willingness to accept ambiguity. It also requires the ability to apply AI as a force multiplier while maintaining rigorous engineering judgment. What you'll be doing: Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them. Co-design noise features with Speed, Power, Reliability, Circuit Design , Power-Arch, ASIC, and platform teams. You're the connective tissue across the codesign web. Work with other team members to define product-level voltage noise targets, drive them to closure, and sign them off at shipment. Build and take ownership of the Sim-to-Si correlation methodology for noise. You know when a model is lying and when silicon is. Model and prototype next-gen noise features — transient sense, droop response, mitigation IP, and codify them so every future program inherits them. Lead show-stopper noise bugs during bringup. The critical issues stop with you. Drive architecture-level codesign tradeoffs across V/F Power Noise Reliability Thermal (Noise-Variation) and (Noise-to-Closure) boundary work, where the highest-leverage innovation lives. What we need to see: BS / MS / PhD in EE, CE, or related (or equivalent experience). 5&#43; years in silicon power integrity, voltage noise, or PDN. Deep expertise in at least one of

Audiovisual Design & Integration Specialist (Experienced or Senior) Company: The Boeing Company Boeing Defense, Space & Security (BDS) / Intelligence Systems (IS) is seeking motivated and self-starting Audiovisual Design & Integration Specialist (Experienced or Senior) for a position based in Herndon, VA . Our team in the Washington, DC Metro region designs, configures, and operates advanced AV systems for U.S. Government customers. Position Responsibilities: Survey, plan, develop, design, configure, and test multi-classification AV solutions for government customers. Generate custom audiovisual system designs, including DSP layouts and systems configuration. Lead or attend customer stakeholder meetings to collect and document or validate system requirements. Research, identify, and recommend technology options to solve customer problems Draft system engineering documentation, including signal flows, line diagrams, bills of materials, rack elevations, and cable plants Support onsite installation of AV systems and lead system configuration phases Coordinate with customer facilities teams and other onsite sub-contractors and vendors during systems installation as required Support the development of end-user training materials and operations & maintenance plans Perform in-house testing and on-site commissioning at client locations Develop expertise in the industry through continuing training, certifications, and review of trade publications Basic Qualifications (Required Skills/Experience): This position requires an active Top Secret/SCI U.S. Security Clearance (U.S. Citizenship Re

NVIDIA silicon runs the world's AI infrastructure. The frequency it delivers across every voltage, process corner, and workload is not assumed. It is measured, correlated, and validated. This role does that work. The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why. You will be the person who follows through between simulation and silicon. When the model is wrong, a frequency corner that doesn't hold, a Vmin that walks, a critical path that timing analysis missed, you find out why, and your data is what the rest of the program acts on. Architecture, design, and product teams do not guess. They use your numbers. The engineers who do this well are rare. They think like circuit designers, work like experimentalists, and reason like data scientists. If that is you, read on. What you'll be doing: Own silicon speed characterization from first power-on through production sign-off, covering frequency, Vmin, Vmax, and timing margins across the full PVT space. Close the correlation gap. Tie pre-silicon timing analysis and critical path predictions to measured silicon, quantify where the model diverges from reality, and produce analysis that architecture and design can act on with confidence. Trace failures to their source, whether a microarchitectural bottleneck, a critical path that doesn't close under voltage, a clocking issue, or a process corner the model didn't anticipate, and drive the resolution. Own and build AI agents that work at your direction: automated test orchestration, intelligent data pipelines, and analysis flows that expand coverage and compress cycle time without sacrificing difficulty. Know where AI accelerates real work and whe

Senior Platform Engineer, Design Automation — US, CA, Santa Clara. Apply via Workday.

Senior Scientist, AI/ML (Biologics Design) — United States - California - Foster City. Apply via Workday.

Build the infrastructure that keeps every NVIDIA chip aligned from first spec to final shipment. NVIDIA's Silicon Co-Design Group sits at the convergence of architecture, silicon, systems, and manufacturing. The System–Manufacturing Architecture (SMAC) team coordinates between system specifications and manufacturing test specifications from pre-silicon POR through production release across GPU, SoC, and CPU programs. When that alignment drifts, silicon faces the consequences: escapes, yield loss, and performance loss. We're hiring a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment, at scale across the full portfolio. The strongest candidates in this role design the workflow before being asked to fix a program, and build the checks and automation that confirm alignment holds long after they've moved on to the next problem. What you’ll be doing: SMAC Workflow Methodology: Define manufacturing spec types, including schema and semantics, derived from system PORs and features. Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle. Production Python Pipelines & Automated Checks: Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs ,ATE, SLT, BLT, L10&#43;, before silicon exposes the discrepancy. The goal is that misalignments surface in the workflow, not on the tester. E2E Program Integration & TPM Attestation: Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag. Alignment can't be assumed; it must be proven at every stage. Agent-Ready Tooling & CI Infrastructure: Integrate tooling into an agent-ready