Silicon Packaging Design Engineer in United States

About Graphcore Graphcore is a global leader in artificial intelligence computing systems. We design advanced semiconductors and data center hardware that deliver the specialized processing power needed to advance AI while improving the efficiency required for broad adoption. As part of SoftBank Group, Graphcore belongs to a family of companies developing some of the world’s most transformative technologies. Our new AI Engineering Campus in Austin will play a central role in building the future of AI computing. The Opportunity We are seeking a system validation engineering intern to help drive server blade and rack validation efforts for next-generation AI infrastructure hardware systems. This role focuses on post-silicon system validation across the full lifecycle of server hardware systems, ensuring functional and performance meets product objectives. You will help drive end-to-end blade and rack validation including development, execution, and debug while collaborating across silicon, firmware, systems, and platform teams. The Blade and Rack Validation team is responsible for ensuring system readiness and quality at scale. The team works cross-functionally with firmware, silicon, and system engineering teams to validate complex AI compute platforms. Type: 12-week summer internship Timing: May - August (exact dates to be confirmed) Commitment: Full-time What You’ll Do Help drive and execute post-silicon validation goals of AI compute blades and racks including testcase planning, development, and automation Help drive validation testcase execution and system debug against program achievements and report validation progress and risks. Drive provisioning and integration of system components (SoC FW, BMC, RMC, OS) for rack-level readiness Triage test failures, collect debug data, and collaborate on root cause analysis. Track validation coverage and continuously improve test processes and infrastructure. What You’ll Bring Working towards a Bachelor's

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Responsibilities and Duties We are seeking a highly skilled System Tests & Diagnostics Engineer to develop, extend, and integrate specialized silicon validation and diagnostics tools for next-generation AI SoCs. Unlike traditional validation roles focused on executing test plans, this position is responsible for developing the diagnostic software and stress tools that expose hardware failures, characterize silicon behavior, and improve platform observability throughout bring-up and validation. You will work closely with Arm engineers to understand and extend existing diagnostics technologies while developing Graphcore-specific capabilities for future AI hardware. Role Summary You will work with existing Arm-developed diagnostics technologies and extend them to support Graphcore's next-generation AI silicon. You will be responsible for developing system-level diagnostics and stress tools that integrate with an existing framework to detect data integrity, computational correctness, performance, and reliability issues across CPUs, AI accelerators, memory, storage, PCIe, firmware, BMC, and other platform components. Examples include silent data corruption (SDC) tests, power transient stress tools, and platform diagnostics, with opportunities to develop new diagnostics as future hardware capabilities evolve. This role requires close collaboration with hardware architects, firmware enginee

Job Details: Job Description: About the Role Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies. What You’ll Do Key responsibilities will include but not limited to: Own physical design and implementation of CPU core blocks or subsystems Execute synthesis, floorplanning, place and route, and design closure Perform static timing analysis (STA), power analysis, and physical verification Drive convergence of timing, power, and area (PPA) metrics Debug and resolve complex design issues across multiple design stages Develop and optimize design flows and automation scripts Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams Contribute to improving design methodologies and best practices Provide guidance to junior engineers where applicable Behavioral traits that we are looking for: Strong problem-solving and analytical thinking Takes ownership and accountability for deliverables Collaborates effectively across multidisciplinary teams Communicates technical concepts clearly and concisely Prioritizes work effectively in a fast-paced environment Continuously learns and applies new tools and methodologies Why Join Us Work on cutting-edge CPU core designs that power client, server, IoT, and AI platforms used worldwide Be part of

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brain of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As a NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA Silicon Codesign Group is seeking a versatile engineer to join the HW bring-up methodology team. The SCG team is uniquely positioned to have an end-to-end view of the product development cycle - from early architecture definition, through bringup, to product release. What will you be doing: Led end-to-end planning and on-time execution of Nvidia's new chip bringup effort, from pre-silicon through production deployment. Coordinate multi-functional teams across Architecture, Build, Validation, DFT, SW, System, and Operations to drive shared bringup achievements. Improve cross-team communication, work, and handoffs. Develop and standardize methodologies, processes, and workflows for silicon bringup, creating reusable checklists and playbooks. Drive scheduling, equipment, and material logistics to support ambitious NPI and production schedules. Lead post-action reviews and convert learnings into concrete process improvements for future silicon and solution bringups. Contribute to post-silicon learnings that feed back into architecture, design, and pre-silicon

Are you ready to contribute to world-class innovation and push the boundaries of what's possible? At NVIDIA, you'll have the opportunity to be part of a team that is driving groundbreaking impacts across various markets. As a Thermal Solutions Development Engineer, you will play a pivotal role in our Silicon Codesign Group, transforming thermal solution concepts into lab-ready builds and beyond. What you will be doing: Build thermal solutions for engineering characterization and validation of next-gen GPU/SOC products, ensuring flawless delivery from concept to lab. Drive end-to-end development and deployment of thermal solutions, collaborating with internal teams and external vendors on build requirements, prototype evaluation, test system integration, and software automation. Improve thermal design processes by incorporating feedback and findings, developing workflow and maintaining our world-class standards. Work closely with system architects, chip and board designers, and software/firmware engineers in a dynamic and high-energy environment to bring industry-defining products to market. Apply AI-enabled approaches and AI tools to accelerate design iteration, test planning, and characterization/validation triage (e.g., requirements/spec summarization, experiment prioritization, log/telemetry summarization, anomaly/outlier detection), improving cycle time, coverage, and traceability while validating outputs against physics, specs, and lab measurements. Partner with AI/tooling teams as the thermal domain SME to define use-cases, success criteria, and evaluation methods; provide feedback to improve tool reliability and usability. What we need to see:

SCG sits at the crossroads of design, architecture, marketing, and productization—owning the journey from the architecture stage through final product definition across Gaming, Datacenter, Automotive, and Embedded markets. As a System Verification CoDesign Engineer, you will work on system-level speed features, develop the verification collaterals and automation infrastructure to characterize and validate them, and lead debug of the complex silicon issues that stand between a program and on-time shipment. This is a hands-on role for an engineer who combines deep technical craft with the drive to compress cycle time using modern tooling—including AI—without losing rigor. What You’ll Be Doing: Collaborate cross-functionally with system architects, hardware, firmware/software, process/reliability, and operations teams to co-design system-level speed features and deliver industry-defining products. Understand system level behavior and speed reliability margins, bounding box constraints and identify solutions that optimize margins . Translate hardware features and architectural requirements into verification techniques that achieve full coverage across testing flows. Perform closed loop validation by correlat ing silicon behavior against timing simulation and design expectations; provide actionable feedback to improve future designs. Define, prototype, and refine pre- and post-silicon bring-up flows to ensure

Job Details: Job Description: Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing. Ready to help build the future of quantum computing? Apply now and be part of this extraordinary journey Key Responsibilities • Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules • Architect qubit and readout element standard cell design and autom

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Engineer at Micron’s HBM New Product Validation team in Boise, ID you will be a senior technical guide responsible for validation strategy and readiness for future-generation High Bandwidth Memory (HBM) products. You will apply deep expertise in complex RAM and high-bandwidth memory architecture and building to establish architecture validation strategies. You will impact decisions that improve validation observability and debug efficiency . You will lead investigations of complex architecture, building , and silicon issues from pre-silicon simulation through post-silicon characterization. You will partner across Design Engineering, Design Validation, Product Engineering, Systems teams, and will develop and promote AI-enabled validation methodologies that improve efficiency, quality, and scalability. Responsibilities: Define architecture-aware validation strategies and coverage direction for future-generation HBM products. Drive validation readiness for next-generation products by preparing strategies, test environments, and execution plans before first silicon, reducing risk, accelerating issue resolution, and preventing late-stage surprises. Evaluate new DRAM/HBM architectural features and define validation requirements and testability needs before DBR. <span style="color:#

We are seeking an exceptional, technically strong, and highly motivated Technical Product Manager to drive NVIDIA's healthcare Physical AI simulation platform. This is a rare opportunity to build foundational enabling technologies at the intersection of physical AI, robotics, simulation, and healthcare, redefining how leading healthcare device and robotics companies develop, train, evaluate, and deploy next-generation Physical AI systems. What You'll Be Doing: Bring innovative physics simulation to healthcare . Identify and integrate advances in physics simulation into enabling technologies that empower healthcare developers to build and validate solutions across robot learning, in-silicon product development, and in-silicon clinical trials—without owning the end applications themselves. Define the product vision and strategy for healthcare Physical AI simulation , spanning classical physics-based and generative simulation, and enabling developers to tackle some of the hardest challenges in healthcare on the path toward Physical AI and in-silicon product development. Develop PRDs with clear technical requirements, benchmarks, product metrics , and evaluation frameworks for simulation fidelity, scalability, policy performance, sim-to-real transfer, and developer efficiency. Lead cross-functional execution across research, engineering, product, developer relations, marketing, and business development to bring new simulation capabilities from research into open-source releases and production adoption. Drive early-access partnerships with healthcare developers, including robotics OEMs and MedTech companies. Translate partner requirements and feedback into detailed platform features and work closely with engineering to deliver them. Help build the horizontal NVIDIA

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary We are seeking a Staff Hardware Engineer to provide advanced operational, diagnostic, and engineering support for Graphcore’s Arm-based hardware platforms across lab and data center environments. This role focuses on supporting hardware bring-up, validation, and troubleshooting of complex AI compute platforms, including server blades, racks, and rack-scale infrastructure. The successful candidate will collaborate closely with engineering, platform, and data center teams to ensure the reliability and performance of next-generation AI systems. The Team The Systems Engineering and Hardware Engineering teams are responsible for enabling the bring-up, validation, and operational reliability of Graphcore’s AI infrastructure platforms. The team works closely with server engineering, firmware teams, platform architects, and data center operations to support the development, testing, and deployment of next-generation AI compute systems. This collaborative environment enables rapid problem-solving and continuous improvement of Graphcore’s hardware platforms from early development through production deployment.

Job Details: Job Description: As a Senior Power and Performance (PnP) Engineer, you will be responsible for PnP product execution focused on measurements, analysis, and projections/estimates of Intel's unlaunched notebook and desktop products. Based on your technical knowledge of both Intel and the competition, you will help influence OEM customers, internal marketing teams, internal engineering teams, debug Intel silicon/platform on PnP issues, and be an integral part for Intel product launches. Core responsibilities to include following: Measure, analyze, and debug workloads to call out any power and/or performance gaps and close with internal engineering teams/architects Measure and analyze SoC/CPU and platform power on a rail by rail basis and debug any issues/gaps Align with other internal engineering teams and architects to ensure there is consensus on power and performance projections/estimates/measurements for both internal and external communication Guide, educate, and influence internal engineering teams, field account teams, and marketing teams on power and performance positioning of Intel products Create power and performance estimates on upcoming Intel products based on workloads to aid marketing decisions and help set internal KPI targets Own the publication of the Power Performance Guide (PPG) collateral to help guide OEM customers Bring up full test platform to enable both power and performance measurements including setup, calibration, and measurements. Qualifications: You mus

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Design Technology Co-Optimization (DTCO) team works at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. The team collaborates closely with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes. As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis. Responsibilities Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment. Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement. Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities. Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues. Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and w