Silicon Power And Characterization Lead in United States

NVIDIA is transforming how the world uses AI, cloud, and accelerated computing, and trust is at the center of that mission. Our Attestation and Trust Services team builds the secure cloud services that show customers their NVIDIA platforms are healthy, resilient, and ready for their most important workloads. In this role, you help design and run services that sit at the intersection of hardware, security, and large-scale distributed systems. We partner closely with security, silicon, platform, and cloud teams to bring new ideas into reliable production services that people rely on every day. We care about building systems that last, supporting each other, and creating space for learning and experimentation. If you enjoy solving complex problems, keeping services running smoothly, and collaborating with teammates from many disciplines, we would love to talk with you! What you’ll be doing: Your main focus will be on building and managing our core attestation cloud services. Day-to-day responsibilities include crafting APIs and integrations, boosting reliability, and working alongside NVIDIA teams to convert hardware trust mechanisms and standards into production-ready solutions. You will contribute significantly to shaping how customers verify that NVIDIA platforms are secure and prepared for their workloads. Crafting and evolving attestation cloud services, APIs, and SDK/CLI integration points that confirm the integrity of NVIDIA platforms across data center, AI, networking, and partner environments. Improving reliability and operational maturity through SLOs/SLIs, alerting, runbooks, incident response, and safe rollout practices. Crafting resilient service behavior that handles dependency failures, caching challenges, regional issues, customer-side resilience needs, and graceful degradation. Architecting trust-material distribution for certificate status, re

About the Team OpenAI Consumer Devices is building the next generation of products that bring powerful AI into people’s everyday lives. Guided by OpenAI’s mission to ensure AGI benefits all of humanity, our team combines world-class researchers, engineers, designers, and operators who care deeply about creating useful, intuitive, and responsible technology. You’ll have the opportunity to work alongside exceptional people on ambitious, zero-to-one challenges at the intersection of hardware, software, and AI. This is a chance to help define an entirely new category of products—and shape how people experience AI in the future. Our team works across custom silicon, embedded systems, operating systems, and cloud services to build reliable consumer devices and the platforms behind them. We connect kernel development with the broader software stack to deliver complete product capabilities. About the Role As an Operating Systems Engineer focused on the Linux kernel, you will design, develop, and maintain the kernel capabilities that underpin OpenAI’s consumer devices. You’ll bring deep expertise in one or more Linux kernel subsystems and carry solutions through the higher-level software stack. Your ownership will extend into the userspace services, libraries, tools, and interfaces needed to deliver complete product features. You’ll shape the boundaries between kernel and userspace, make design decisions across the stack, and see your work through development, integration, and production. In this role, you will: Build kernel capabilities: Design, implement, and maintain Linux kernel subsystem changes that support device capabilities and product requirements. Own features across the stack: Choose appropriate kernel and userspace boundaries, and build the interfaces and supporting components needed to deliver reliable features in shipped products. Debug complex system behavior: Use tracing, profiling, instrumentation, and diagnostic tools to resolve correctness, concurrency, p

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building next-generation processors and systems, bringing together world-class expertise across silicon, systems, and software. We are looking for a CPU Performance Modeling Architect to help evaluate, shape, and optimize the performance of future CPU architectures. In this role, you’ll use performance modeling, workload analysis, and deep understanding of CPU architecture to answer complex questions about how a processor should be designed. You’ll work closely with CPU architects, RTL designers, software and compiler teams, and system engineers to identify performance opportunities, evaluate architectural tradeoffs, and turn modeling insights into actionable design decisions. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A CPU architect, performance architect, or performance modeling engineer with experience influencing CPU architecture or microarchitecture decisions. You have a strong understanding of modern processor architecture and enjoy digging into why a CPU performs the way it does. You are comfortable combining hardware architecture, software, data, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a Timing Engineer to join our silicon team. In this role, you’ll drive static timing analysis and closure for complex, high-performance designs. You’ll collaborate closely with logic, DFT, and physical design teams to debug constraints, optimize paths, and ensure our chips meet performance targets across corners and modes. This role is hybrid , based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA . We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are Experienced in STA and passionate about enabling silicon to meet aggressive performance goals. Analytical and detail-oriented, with a strong understanding of timing paths, constraints, and optimization strategies. A collaborative team player who works well across logic, DFT, and physical design boundaries. Resourceful and self-driven, capable of developing scripts and methodologies that improve timing closure workflows. What We Need 7+ years of industry experience and a proven record of successful tapeouts. Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis. Proficiency in writing and debugging SDC constraints, creating ECOs, and

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building cutting-edge processors and systems for AI workloads, bringing together world-class expertise in silicon, systems, and software. We are seeking an experienced Technical Program Manager to lead cross-functional product development efforts and drive complex programs from concept through execution and delivery. This role is ideal for someone who thrives in highly collaborative environments, excels at bringing teams together around a common goal, and has a track record of delivering complex hardware products on schedule. This role is hybrid, based out of Santa Clara, CA, Austin, TX, or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You are an experienced program leader with a strong technical background and a proven ability to drive complex product development efforts. You excel at building alignment across diverse teams and can influence stakeholders at all levels of the organization. You are highly organized, proactive, and comfortable managing ambiguity while balancing multiple priorities. You are a strong communicator who can translate technical challenges into actionable plans and executi

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking a SoC Physical Design Verification Engineer to drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes. You’ll lead physical verification closure (DRC, LVS, ERC, etc.), debug issues using standard industry PV tools, and collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts. If you thrive in a fast-paced environment and enjoy solving complex challenges in cutting-edge silicon, we’d love to hear from you. This role is hybrid , based out of Santa Clara, CA or Austin, TX or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. A mentor and technical leader passionate about building efficient, manufacturable silicon. What We Need BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verif

1671 About the Role We are seeking a Senior Signal Integrity Engineer to develop, validate, and optimize high-speed signaling solutions across blade- and rack-level architectures for advanced compute platforms. This role sits at the intersection of silicon, package, interconnect, board, and system design , with a strong emphasis on hands-on measurement, simulation correlation, and cross-functional technical communication. Key Responsibilities End-to-end signal integrity analysis for blade- and rack-level system architectures. Analyze and optimize high-speed and low-speed I/O interfaces, including PCIe Gen4/5/6, Ethernet, DDR, SerDes, SPI , I2C, etc . and related interconnects. Perform time-domain and frequency-domain simulations using tools such as Ansys HFSS, Keysight ADS, Cadence Sigrity, CST, SPICE , or similar. Support hands-on lab validation using VNA, TDR, BERT, and high-speed oscilloscopes . Correlate simulation results with lab measurements to identify margin gaps, debug issues, and improve design methodology. Collaborate with silicon, package, board, connector, cable, and system design teams to optimize I/O channel performance. Work with interconnect vendors and ODMs to guide board layout, stack-ups, routing rules, and system design decisions. Review schematics, layouts, simulation results, and validation data for blade, backplane, and rack-level hardware. Prepare and communicate clear validation reports, measurement summaries, debug findings, and technical recommendations to internal teams, vendors, and senior technical stakeholders. Required Qualifications Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field . Strong experience in signal integrity for high-speed digital systems. Hands-on measurement expertise using VNAs, TDRs, BERTs, and high-speed oscilloscopes . Experience measuring and analyzing S-parameters, impedance profiles, eye diagrams, jitter, timing margins, insertion loss, return loss, and cro

About Ema Ema is building the world’s leading Agentic AI platform to transform enterprise productivity. We enable organizations to delegate repetitive tasks to Ema, the Universal AI Employee, delivering 10x gains in workforce efficiency, across functions. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production — we ship real systems that run real business processes at scale. About the Role Ema sells through two motions that behave very differently, and today they share one pipeline, one CRM, and one forecast. Direct enterprise — field Account Executives landing Fortune 2000 logos at $250K+ initial contract value and expanding past $500K, into buying committees that include IT, security, data governance, and procurement. Partner-led — global systems integrators and ISVs, including Teleperformance, PwC, Wipro, NTT Data, Hitachi, KPMG, Atos, ADP, Microsoft, and Google, who deploy Ema's Frontier Apps to their own clients. In some cases the partner embeds Ema inside their own product and owns the end-client relationship entirely. Those two motions require different definitions, different attribution rules, and different quota treatment. Building that distinction — and the systems, reporting, and compensation logic that sit on top of it — is the core of this role. This is the first dedicated Revenue Operations hire supporting the US go-to-market organization. You will be building the function, not maintaining one. What You Will Own Forecasting and pipeline management Own the weekly forecast process and cadence across direct and partner motions, and report fo

Job Details: Job Description: This is a high-visibility, commissioned sales leadership role within Intel's US Sales organization, specifically focused on our most disruptive AI-Native and Strategic CSP accounts. You will be the primary architect of Intel's relationship with industry titans who are redefining the boundaries of AI model training, AIaaS solutions and deployment at scale. This is not a traditional sales role. You will operate at the intersection of deep technical engineering and executive business strategy, ensuring Intel's silicon and software roadmap aligns with the world's most demanding AI-as-a-Service and SaaS platforms across on-prem, Tier1 CSP and NeoCloud environments. Key Responsibilities Executive Orchestration: Act as the One Intel lead, building deep-rooted partnerships with C-suite executives and Principal Engineers at world-class AI and SaaS firms. Technical Value Synthesis: Translate complex hardware architectures (CPU, GPU, Accelerator, Networking, and Packaging) into business outcomes for customers running massive-scale distributed training and inference workloads. Strategic Growth: Drive Intel's data-centric growth strategy by identifying and securing design wins within the core infrastructure of the world's leading AI models and solution providers. Cross-Functional Leadership: Partner closely with Cloud Solution Architects (CSAs), Intel Business Units, Cloud and OEM partners to influence future product roadmaps based on the unique needs of AI-native disruptors. Market Evangelism: Serve as a technical and business evangelist, articulating Intel's vision for the future of AI and compute infrastructure in a highly competitive landscape. <p style="text-align:inhe

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. What you'll be doing: As a senior member in our team, you will work with pre-silicon and post-silicon data analytics - visualization, insights and modeling. Design and uphold sturdy data pipelines and ETL processes for the ingestion and processing of DFX Engineering data from various origins Lead engineering efforts by collaborating with cross-functional teams (execution, analytics, data science, product) to define data requirements and ensure data quality and consistency You will work on hard-to-solve problems in the Design For Test space which will involve application of algorithm design, using statistical tools to analyze and interpret complex datasets and explorations using Applied AI methods. In addition, you will help develop and deploy DFT methodologies for our next generation products using Gen AI solutions. You will also help mentor junior engineers on test designs and trade-offs including cost and quality. What we need to see: BSEE (or equivalent experience) with 5&#43;, MSEE with 3&#43;, or PhD wi

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati

Job Details: Job Description: As a Material Analysis (MA) Technician, you will be part of a Technology Development (TD) and High-Volume Manufacturing (HVM) lab responsible for performing material analysis and failure analysis in support of Intel's silicon process development and high-volume production. You will work on developing imaging, composition analysis and sample preparation techniques, and best-known methods (BKMs) to improve lab analysis quality, efficiency and output. You will directly interface with TD and HVM fab customers and quality/reliability engineers to develop solutions to problems by utilizing lab capabilities. The scope may include wafer and unit level, front-end modules and back-end/far back-end modules. Responsibilities may include but not be limited to: • Conducting hands-on analysis by effectively utilizing lab techniques, from sample prep micro-cleaver, ion mill etcher, mechanical polish to SEM/EDX, Dual beam FIB, TEM techniques to characterize Si fabricated structures at nanometer scales and integrated circuit device to improve process, performance and reliability; and to identify physical failure mode toward the root-cause identification. • Conducting hands-on data collection with various lab equipment’s, and assisting engineers to implement materials characterization techniques to determine fundamental thin film material structure/properties and to collaborate with process development engineers across functional areas and organizations to improve process performance and reliability. • Supporting and sustaining lab equipment. Ensuring that lab analytical capabilities needed to support advanced transistor and interconnect technology and/or product development are in place. Cooperating with other lab areas beyond local MA/FA (Failure Analysis) labs to achieve

Job Details: Job Description: This position is in the Intel Mask Operations within the Logic Technology Development team working in one of the most advanced semiconductor process technologies in the world. In this position the engineer will be an integral contributor to the ongoing production of photolithography masks for Intel's leading-edge silicon manufacturing solutions. In this position, you will work on-site, in a dynamic and collaborative environment solving complex and challenging technical problems on sophisticated manufacturing processes and equipment. As IMO module Engineer the responsibilities may include but not limited to: Process equipment installation and development. Equipment maintenance, management of troubleshooting activities, regular monitoring of process performance, defect analysis and reduction. Drives improvements on quality, reliability, cost, yield, process stability/capability, productivity, and safety/ergonomics. Working with cross functional teams to solve technical process and defect issues. Plans and conducts experiments to fully characterize the process throughout the development cycle. Establishes control systems to optimize and sustain production performance. Develops strategies to resolve difficult problems and establishes systems to manage these problems in the future. An ideal candidate should exhibit the below behavioral traits: Experience with rapid analysis of complex process issues and identification of a solution path Willing to work Independently with minimal direction, to be self-directing and show initiative Communication skills and demonstrated ability to summarize complex d

About Ema Ema is building the world’s leading Agentic AI platform to transform enterprise productivity. We enable organizations to delegate repetitive tasks to Ema, the Universal AI Employee, delivering 10x gains in workforce efficiency, across functions. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production — we ship real systems that run real business processes at scale. What You'll Own As our Social Media & Founder Brand Manager, you'll sit at the intersection of content, brand, and experimentation. You'll shape how the world sees Ema and its founders — building a distinctive, high-reach presence across LinkedIn, X, YouTube, and beyond, in the fastest-moving category in tech: agentic AI. Social Media & Content Creation Scale Ema's LinkedIn from 130K → 200K+ with bold, creative storytelling and a strong lens on ICP Maintain a consistent 4-week rolling calendar across social media, blogs, and newsletter channels — while staying nimble enough for moment marketing: hopping on relevant tech trends and conversations in real time, especially for the founders Create compelling video content for both Ema and the founders — from short-form clips and talking-head videos to event and product moments — built natively for each platform Work with design to repurpose existing content — whitepapers, blogs, interviews, videos — into carousels, short videos, threads, and newsletters to achieve consistency + repetition as a brand Continuously experiment with and improve existing channels, and identify the right new distribution channels and formats to scale E

About Ema Ema is building the world’s leading Agentic AI platform to transform enterprise productivity. We enable organizations to delegate repetitive tasks to Ema, the Universal AI Employee, delivering 10x gains in workforce efficiency, across functions. Founded by former executives from Google, Coinbase, Flipkart, and Okta, our team includes engineers from premier tech companies and graduates of Stanford, MIT, UC Berkeley, CMU, and IITs. We are backed by industry leading investors including Accel, Naspers/Prosus, Section32, and angels like Sheryl Sandberg and Dustin Moskovitz. Headquartered in Silicon Valley and with offices in London, Bangalore and Vancouver, Ema is at the frontier of what Agentic AI can do in production — we ship real systems that run real business processes at scale. At Ema, we build AI Employees that operate inside the enterprise. Healthcare is where the bar is highest: the output has to be accurate, auditable, and clinically sound. We're opening a part-time role focused on agent measurement and improvement. You'll instrument how our healthcare AI Employees perform in production, identify where quality breaks down, and design the experiments that close the gap — partnering with clinical experts to ensure improvements translate into better patient outcomes, not just better metrics. We're looking for strong analytical judgment (Python, agent lead development), comfort operating with incomplete information, and genuine interest in the healthcare domain. Clinical experience is valued but not required. This engagement is structured as a paid internship or contract engagement, with weekly syncs in our Bay Area office. Compensation offered will be determined by factors such as location, level, job-related knowledge, skills, and experience. Certain roles may be eligible for variable compensation, equity, and benefits. Ema Unlimited is an equal opportunity employer and is committed to providing equal employment opportunities to all employees and applic