Hardware Platform Security Architect in Bengaluru

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Debug Validation Lead will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The Team The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems. The

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software, and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers, and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to the Validation leadership team, the Principal Execution and Quality Validation Engineer will be responsible for driving validation execution, automation, product quality, and release readiness across Graphcore silicon and platform technologies. The role combines deep expertise in hardware validation, test automation, and quality engineering with a strong focus on execution excellence. Working closely with architecture, design, verification, firmware, software, systems engineering, and validation teams, the successful candidate will develop scalable validation methodologies, improve test coverage and execution efficiency, and ensure products meet the highest standards of functionality, reliability, and performance before customer deployment. As a recognized technical leader within the validation organisation, this role will influence validation strategies, automation roadmaps, and quality practices across multiple projects and engineering disciplines. The Team The Validation Execution and Quality team sits within the Validation organisation and is responsible for improving validation effectiveness, te

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to senior leadership within Architecture and Validation, the Debug Validation Engineer will drive post-silicon debug and validation activities for next-generation AI compute silicon and systems. The role is responsible for leading teams focused on identifying, reproducing, analysing and resolving complex silicon, firmware and system-level issues during bring-up, characterization and product readiness. This position combines deep technical debugging expertise with strong cross-functional collaboration across multiple engineering disciplines. The role will work closely with architecture, RTL, firmware, software and systems teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The role will work closely with architecture, RTL, firmware, software, systems and platform teams to improve debug methodologies, accelerate issue resolution and strengthen validation coverage. The Team The Post-Silicon Debug and Validation team sits within the Architecture and Validation organisation and is responsible for bring-up, debug and validation of Graphcore silicon and systems.

About us Graphcore is one of the world’s leading innovators in Artificial Intelligence compute. It is developing hardware, software, and systems infrastructure that will unlock the next generation of AI breakthroughs and power the widespread adoption of AI solutions across every industry. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Together, they share a bold vision: to enable Artificial Super Intelligence and ensure its benefits are accessible to everyone. Graphcore’s teams are drawn from diverse backgrounds and bring a broad range of skills and perspectives. A melting pot of AI research specialists, silicon designers, software engineers, and systems architects, Graphcore enjoys a culture of continuous learning and constant innovation. Job Summary Reporting to the Validation leadership team, the Senior Execution and Quality Validation Engineer will be responsible for executing validation plans, developing automation solutions, and improving product quality across Graphcore silicon and platform technologies. Working closely with architecture, design, verification, firmware, software, systems engineering, and validation teams, the successful candidate will contribute to scalable validation methodologies, improve test coverage and execution efficiency, and help ensure products meet high standards of functionality, reliability, and performance before customer deployment. The role requires strong technical skills, attention to detail, and a passion for improving validation quality through effective execution, automation, and continuous improvement. The Team The Validation Execution and Quality team sits within the Validation organisation and is responsible for improving validation effectiveness, test execution efficiency, product quality, and release readiness across Graphcore silicon and platform products. The team develops validation methodologies, automation

Secure Every Identity, from AI to Human Identity is the key to unlocking the potential of AI. Okta secures AI by building the trusted, neutral infrastructure that enables organizations to safely embrace this new era. This work requires a relentless drive to solve complex challenges with real-world stakes. We are looking for builders and owners who operate with speed and urgency and execute with excellence. This is an opportunity to do career-defining work. We're all in on this mission. If you are too, let's talk. Description We are seeking a ServiceNow ITAM Developer to join our ServiceNow Platform Team. This role is a key driver in our mission to manage the full lifecycle, compliance, and financial impact of our global technology footprint. You will serve as the technical SME for Software Asset Management (SAM) and Hardware Asset Management (HAM), ensuring our platform delivers an accurate, real-time view of asset visibility and cloud consumption. This is a highly collaborative and integrated role. You will work closely with our SAM Managers to translate complex asset management business processes into technical solutions that identify and capture cost-saving opportunities. You will manage a sophisticated ecosystem that connects financial data from Workday and NetSuite, procurement data from Coupa, and endpoint data from JAMF and Intune. Your expertise will bridge the gap between technical data modeling and strategic business outcomes. Responsibilities Lead technical delivery for ServiceNow SAM and HAM, focusing on the Content Library, Normalization engines, and Reconciliation processes. Partner with business stakeholders to analyze asset management business processes and implement automated workflows that drive license reclamation and cost-avoidance strategies. Oversee and troubleshoot complex integrations with core systems, including Coupa, Okta, JAMF, and Intune, ensuring data flow is consistent and accurate. Build, configure, and maintain integrations with SaaS

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We’re looking for a hands-on RTL Design Engineer to own the microarchitecture and RTL implementation of the Power Management Subsystem/Interrupt Controllers/AXI Interconnect/Cache Controller . You’ll collaborate with cross-functional teams—architecture, firmware, software, DV, and PD—to define, design, and optimize power management solutions for next-generation RISC-V/ARM-based SoCs. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels. During the interview process, you will beevaluated and offered a level that aligns with your experience, which may differ from the one in this posting. Who You Are 5–10 years of experience in ASIC/SOC/IP design, with hands-on experience in microarchitecture and RTL development Skilled in Verilog/SystemVerilog and comfortable working across design, debug, and analysis Design and develop microarchitectures for a set of highly configurable IPs Microarchitecture and RTL coding ensuring optimal performance, power, area Work with verification teams on assertions, test plans, debug, coverage, etc. Deep understanding of power management concepts—clocking, reset, DVFS, and low-power modes Familiar with RISC-V or ARM-based SoCs and standard bus protocols (AXI, AHB, APB, CHI) Awareness of functional safety (ISO 26262) practices in hardware design What We Need Abil

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is building the future of AI compute, and this role will build the talent pipeline that makes it possible. As an Early Talent Recruiter, you will own university and early-career recruiting for your site, shaping which schools we invest in, building relationships with students and faculty, and leading intern, co-op, and new-grad hiring from first outreach through accepted offer. You will not simply run an existing campus calendar. You will decide where to focus, raise the quality of the funnel, and build the recruiting motion that our growing hardware and software teams need. This role is hybrid, based out of Tokyo, Japan, Bangalore, India, or New Taipei City, Taiwan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You have owned a full campus recruiting cycle, including school selection, university partnerships, sourcing, screening, interview coordination, offer management, and closing. You use judgment and influence to partner with hiring managers, challenge assumptions when needed, and hold a clear hiring bar without relying on authority. You work from funnel data and can connect measures such as applications, conversions

Job Summary Reporting to the Memory Validation leadership team, the Senior Silicon DDR/HBM Validation Engineer will be responsible for the bring-up, validation, characterization and debug of advanced memory subsystems used in next-generation AI compute platforms. The role will focus on DDR and HBM technologies, working closely with silicon design, firmware, characterization, platform and systems teams to ensure robust memory subsystem functionality, performance and reliability. The successful candidate will take ownership of significant validation activities, contribute to debug and root-cause analysis efforts, and help improve validation methodologies, automation and infrastructure. The Team The Memory Validation team sits within the Validation organisation and is responsible for the bring-up, validation, characterization and debug of memory subsystems across Graphcore silicon and platform products. The team supports DDR and HBM validation activities throughout the product lifecycle, from first silicon through production readiness. Engineers work closely with architecture, RTL, firmware, characterization, systems and platform teams to ensure memory technologies meet functionality, performance, reliability and performance objectives. Responsibilities and Duties Execute validation and bring-up activities for DDR and HBM memory subsystems Verify memory bring-up software, firmware and scripts against defined project requirements Debug firmware, hardware and system-level issues and contribute to root-cause analysis activities Analyse system logs, validation data and characterization results to identify failures and performance issues Perform PHY characterization and analog-level analysis during stress testing and validation activities Develop and execute functional, stress, performance and corner-case validation tests Perform signal integrity, voltage, frequency and timing measurements using laboratory instrumentation Char

About the Role At Together AI, you’ll build and operate one of the world’s largest GPU fleets used for frontier model training and inference. This isn’t a traditional infrastructure role—we’re looking for engineers who love building systems, automating everything, and solving problems at massive scale. If you enjoy writing software more than clicking dashboards, obsess over eliminating manual work, and want to build infrastructure that manages tens of thousands of GPUs autonomously, we’d love to talk. Responsibilities Design and build fleet automation systems that provision, validate, deploy, upgrade, repair, and retire GPU clusters with minimal human intervention. Build AI Infrastructure Agents that automate deployment, root-cause failures, incident triage, and autonomous remediation. Develop Fleet Intelligence platforms that continuously monitor hardware health, firmware, networking, storage, thermals, and workload performance to predict failures before they impact customers. Build software that maximizes GPU availability, utilization, performance, and reliability across thousands of accelerators. Create automated validation systems for GPUs, InfiniBand/RoCE fabrics, NVLink/NVSwitch, storage, and distributed AI workloads. Build internal platforms and developer tools that allow infrastructure to be managed through software—not manual operations. Continuously improve deployment velocity, reliability, and operational efficiency through automation. Partner closely with hardware, networking, platform, and AI teams to push the limits of AI infrastructure. Requirements 3+ years building distributed systems, infrastructure platforms, or large-scale backend software. Strong software engineering skills in Python, Go, or Rust . Experience building platforms, automation systems, or developer infrastructure. Experience with Linux, Kubernetes, Terraform, Ansible, or similar infrastructure technologies. Strong systems thinking with the ability to understand problems across hardw

Job Details: Job Description: Intel India Customer Engineering Team is in a mission to create successful Original Design Manufacturers (ODMs) from India across their customer base. We are seeking a Hardware Board Design Engineer specializing in Power Delivery design and debug experience to help Intel customers design and debug their hardware platforms based on Intel Core and Atom CPUs. Qualifications: • Education : Bachelor's or Master's degree in Electronics/Electrical Engineering or related field • Experience : 7-12 years of industry experience (preferably 5-6 years designing and debugging hardware boards with Power Delivery focus using Intel Core/Atom CPUs) • Power Delivery Expertise : Deep understanding of system Power Delivery requirements and familiarity with Intel Core/Atom processor Power Delivery guidelines including IMVP specifications and PDN analysis • Circuit Design : Extensive experience with Buck, Boost, and Multi-phase Power Delivery Network design, including control loop understanding and very high current/low-voltage power delivery design • Design Tools : Proficiency in schematic capture using ind

NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. Today, we are tapping into the unlimited potential of AI to define the next era of computing. As an NVIDIAN, you will address challenges spanning architecture, silicon, firmware, software, and production — and excellent judgment matters as much as technical depth! Every major NVIDIA silicon product family—from the chips powering AI and datacentre systems to gaming, professional, embedded, and automotive platforms—passes through our productization work on its way to production. NVIDIA’s Silicon Co-Design Productization team works from pre-silicon strategy and feature development through bring-up, characterization, correlation, and optimization. Our charter spans power & performance modelling, bring up & tuning of low-power features, power & thermal controllers , and system-level optimization that ultimately shape how NVIDIA products are configured, binned, specified, and shipped. What you'll be doing Drive silicon power productization from pre-silicon planning through bring-up and production, including test strategy, feature readiness, characterization, and optimization. Partner with architecture and design teams to identify improvements, validate features, and help translate them into production-ready solutions. Correlate measured silicon behaviour with pre-silicon expectations, investigate gaps, and drive complex issues to root cause. Build power and performance models and characterization methodologies that decide silicon binning, product specifications, productization decisions, and customer guidance. Use AI/ML and data-driven methods to analyse characterization & telemetry data, identify anomalies & trends , and accelerate issue debug across silicon, board, power delivery, firmware,

Staff Embedded SW/FW Engineer (Bringup) Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. We are opening a new AI Engineering Campus in Bengaluru which will play a central role in Graphcore's work building the future of AI computing. Job Summary We have an exciting opportunity to be part of a collaborative, cross-functional development team developing C code used to validate cutting-edge, high-performance AI chips and platforms. You will play a critical role in supporting new product introductions and post-silicon validation. Working within the Post-Silicon Bringup team, you will be involved with bringing first silicon to life, developing code primarily in C to configure and exercise systems and sub-systems on new silicon devices, and working closely with many other teams to help it become a fully characterised and working product, reporting project status/progress to program management on a regular basis. You will have the opportunity to, and be responsible for, leading, mentoring, and providing technical guidance to other engineering team members. In this role, you can leverage your experience and industry knowledge to architect and drive implementation of continuous improvements to test infrastructure and processes. The Team The Post-Silicon Bringup team sits within the Architecture and Validation team, we are responsible for bringup and validation of new silicon when it returns from manufacture, enabling and supporting the production SW and FW teams to bring up their software and supporting the Silicon Characterisation team. Respons

Job Details: Job Description: We are seeking an experienced Analog Design and Infrastructure DA Manager to lead the development, deployment, and governance of analog/mixed-signal design environments and CAD infrastructure. This role owns EDA tool ecosystems, PDK integration, compute infrastructure, design data governance, and tapeout manifest management to ensure high productivity, reproducibility, and audit readiness across silicon programs..The ideal candidate combines deep analog/mixed-signal design flow and e-test structure development expertise with strong infrastructure leadership and disciplined configuration/data management practices. Key Responsibilities-1. Analog Design Environment and Flow Management-Own and maintain analog and mixed-signal design flows using platforms such as Virtuoso ,Develop and maintain schematic, layout, verification, and extraction flows (LVS, DRC).Support simulation environments including HSPICE, Corner analysis.Drive automation and methodology improvements to reduce turnaround time and increase design robustness. 2. Infrastructure and Compute Management Oversee Linux-based DA infrastructure including compute farms, storage systems, and license servers (FlexLM). Manage LSF/grid environments and job scheduling systems. Ensure scalability, system monitoring, high availability, and performance optimization. Partner with IT on hardware lifecycle planning, cloud integration, and disaster recovery. Maintain secure, access-controlled design environments aligned with IP protection policies. 3. Design Data, Manifest and Configuration Management Design Data Governance Manage large-scale analog design libraries, hierarchical database structures, and technology libraries. Define backup, archival, and retention policies for tapeout-critical data. Implement data integrity validation and corruption prevention controls. Oversee distributed stor

Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we’re looking for exceptional talent to reimagine the way the world works. Instawork Robotics Labs (IRL India) · Bengaluru · Internship (Full-time, On-site) Build the hardware that teaches robots about the real world Robots learn from data — and the best data comes from the real world, captured at scale. At IRL India, we’re building Instacore, our proprietary 5-camera + IMU wearable capture rig that records rich, egocentric video of humans doing real tasks in real environments. Hundreds of these units run across India every day, feeding the training pipelines of frontier Physical AI models. Your job : keep this fleet alive, fast, and growing. If you’ve spent nights in a workshop before a Robocon run, wrenched on a Formula Student or BAJA vehicle, or built anything that had to actually work under pressure — this role was designed for you. What you’ll do Own uptime for the Instacore fleet. Build, assemble, test, and troubleshoot the mechanical and electrical systems that keep hundreds of units capturing data daily. Ship hardware iterations fast. Work directly with our robotics team to prototype, integrate, and stress-test improvements to the rig — cameras, IMUs, wiring, mounts, power Get your hands dirty. Sensors, actuators, controllers, soldering irons, 3D printers — this is a workshop role, not a slideware role. Travel and deploy. Set up hardware hubs across India and APAC. You’ll see your work running in the field, not just on a bench. Debug like a detective. Trace faults through hands-on testing, fix them, and document what you learned so the fleet gets more reliable every we

Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we’re looking for exceptional talent to reimagine the way the world works. Quality Control Intern – Hardware Bengaluru, Karnataka, India Instawork is on a mission to create meaningful economic opportunities for skilled hourly professionals in communities around the globe. Our AI-powered labor marketplace helps local businesses scale, and enables global technology companies to push the frontiers of robotics and AI. Backed by world-class investors like Benchmark, Spark Capital, Craft Ventures, Greylock, Y Combinator, and others, we're looking for exceptional talent to reimagine the way the world works. Role Overview The Quality Control Intern – Hardware is the checkpoint every recording rig passes through, in both directions. When rigs return from the field, you inspect their condition, run a functional check, and capture a short test recording that you review to confirm the cameras, footage, audio, and storage are all working. Before any rig goes back out, you give the final sign-off that it is field-ready. This is a small role with an outsized impact: a rig that leaves your desk in a bad state means a Field Officer travels to a business, records for hours, and returns with unusable or missing data — a full day lost, and sometimes a burned business relationship. Your job is to make sure that never happens. Precision, consistency, and discipline are the whole game here. What You'll Own Nothing goes to field without your approval; nothing comes back without your inspection and log. You are the last line of defense on rig quality before it reaches a business. Key Responsibilities 1