Staff Engineer, RTL Design

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Complete ownership of verification and end to end analysis of complex block level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5, DDR6 and LPDDR6 that are capable of operating at high speeds of up to 11,4000MT/s. Staff-Level Expectations: At the Staff level, engineers are expected to: Lead verification efforts for strategic IPs and complex subsystems. Influence verification methodology across projects. Mentor junior engineers and drive verification quality, productivity, and innovation. Provide technical leadership across geographically distributed teams. Ability to lead team, guide and set the direction for the verification effort for any project that the team undertakes. Define roadmap and future scope of verification methodologies. Roles and Responsibilities: Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM) Run directed and constrained-random tests and regressions; analyze results and triage failures. Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout

About Us Graphcore is a globally recognised leader in Artificial Intelligence computing systems. The company designs advanced semiconductors and data centre hardware that provide the specialised processing power needed to drive AI innovation, while delivering the efficiency required to support its broader adoption. As part of the SoftBank Group, Graphcore is a member of an elite family of companies responsible for some of the world’s most transformative technologies. Job Summary Working within the logical design team, the silicon logical design engineer is responsible for a wide range of logical design tasks. The team is responsible for delivering the Microarchitecture and RTL design to implement the chip architecture specification for Graphcore Silicon, working closely with other engineers within the Silicon team. The successful candidate will be responsible for helping the team deliver high quality micro-architecture and RTL for Graphcore chips, working within the logical design team and with the broader Silicon team to ensure we meet the company objectives for Silicon delivery. Responsibilities and Duties Integrate IP and subsystems into top-level SoC designs Develop and maintain build and configuration environments Perform synthesis, linting, CDC/RDC, and timing checks at the SoC level Support verification and physical design teams through clean interface hand-offs Debug and resolve integration-related issues across multiple hierarchies Contribute to the continuous improvement of integration flows and automation Producing high quality microarchitecture and other documentation Ensure good communication between sites to maintain consistent working practises Candidate Profile Essential skills: Logical design experience in relevant industry Experience range 8-12 years in Semiconductor Industry/Product development exposure. Be highly motivated, a self-starter, and a team player Ability to work across teams and debugging issues seen to find root cau

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff Design Engineer in the Non-Volatile Memory Core Functional Group , you will design and optimize critical Flash memory circuits such as row/column drivers, sense amplifiers, and associated core circuitry , with focus on performance, power, area, timing, and reliability . Responsibilities Own block and subsystem-level circuit design, optimization, verification, and layout supervision . Optimize designs from base-cell to full-chip level using HSPICE, FastSPICE, NC-Verilog, and related tools. Collaborate with Logic/RTL teams to define array functionality and develop efficient Analog/Mixed-Signal (AMS) architectures combining custom circuits and digital techniques. Work with Technology and project teams on array waveforms, circuit integration, and full-chip floorplanning. Use scripting, automation, and AI/Agentic AI technologies to accelerate design, simulation, validation, and engineering productivity. Develop and maintain Micro-Architecture Specifications (MAS) and required design documentation, including ISO 26262 compliance where applicable. Provide technical guidance and mentor junior engineers . Requirements MS/PhD with 2–6 years or BS with 6–10 years of relevant semiconductor experience. Strong knowledge of analog, digital, and mixed-signal circuit design, CMOS device physics, Flash/NAND architecture, and reliability . <l

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff Engineer: STA Methodology & Sign-off Lead We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges. This is a critical role for a forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out. The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes. Flow Development & Left-Shift Automation: Architect, deploy, and maintain adva

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Be part of ASIC Design Verification team responsible for verification of IP/Block or Subsystem. Roles & Responsibilities: • To be part of a highly skilled ASIC Team working on latest technologies • Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off • Ability to lead and mentor a team of verification engineers • Ensure first pass product through verification coverage and sign-off criteria • Pair with similar domain specialists across other geographical locations on core technical initiatives Minimum Qualifications: • M.S./M.Tech, BS/BE (Electronics) with 10&#43; Years of experience • Should have expertise in IP/Block/Subsystem level verification • Experience with AMBA protocols like AXI/AHB • PCIe/NVMe/DDR protocol knowledge and work experience on DDR/PCIe/NVMe controllers or similar IPs • Proven track record of building Verification Plan, UVM Environment and Test Benches • Experience with RTL debugging, Scoreboard, Assertions, Functional coverage coding and Code Coverage analysis • Sound knowledge of Verilog and System Verilog languages • This position requires good written and verbal communication skills as well a strong commitment and ability to work in cross functional and global teams Preferred Qualifications: • NVMe protocol knowledge and experience with working on NVMe contro

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. At Tenstorrent, we build open, state of the art compute for real workloads and real developers.You will own CPU core‑level verification, shaping how our out‑of‑order RISC‑V CPUs behave in silicon. This role is hybrid, based out of Bangalore, India. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are You bring 8+ years in CPU verification or closely related digital design. You know high‑performance out‑of‑order CPU microarchitecture in depth. You work comfortably with RTL, waveforms, logs, and complex debug scenarios. You communicate clearly across design, DV, emulation, and post‑silicon teams. What We Need Plan and drive functional verification for CPU core features and complex microarchitectural scenarios. Develop UVM, assembly, and C/C++ based stimulus, functional models, and coverage for ISA, RISC-V extensions, and un-core components. Debug simulation and emulation regressions using RTL understanding, waveforms, and logs to identify and resolve issues efficiently. Build and enhance coverage models, testbenches, and debug infrastructure to improve verification quality and coverage closure. Collaborate with design, validation, and