Advance Packaging Process Development Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. You will also work on efforts to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing coll

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As an HBM Power Delivery Network (PDN) Engineer , you will be part of the Heterogeneous Integration Group (HIG), responsible for the design, analysis, and optimization of power delivery networks for next-generation HBM products. You will work closely with architecture, design, physical design, packaging, and product engineering teams to ensure robust, efficient, and manufacturable power delivery solutions that meet aggressive performance, power integrity, and reliability targets. This is a hands-on technical role focused on PDN design, EM/IR analysis, and cross-domain optimization across technology, design, and layout. Key Responsibilities Design and develop SoC-level and HBM-cube-level power delivery networks for HBM designs, including power grid architecture, routing strategies, and decoupling schemes. Perform EM/IR analysis and optimization using industry-standard tools (e.g., Cadence RedHawk, Ansys Totem) to ensure power integrity across dynamic workloads. Collaborate with physical design teams on floorplanning, placement, and routing strategies to enable efficient PDN implementation. Drive power integrity closure across multi-mode/multi-corner scenarios, identifying and mitigating droop, noise, and electromigration risks. Work with package and system teams to co-optimize die-package-system PDN interactions, including bump/pad assignment and current distribution. Develop and validate power models, including activity-based current profiles and transient analysis for realistic

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII. You will work closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA (performance, power, area) and robust signoff collateral for tape-out. This is a hands‑on role with opportunities to own blocks or top‑level integration across multiple product generations. Key Responsibilities Own physical implementation for SoC blocks and/or top-level, including floor-planning, placement, CTS, routing, and physical optimization to meet PPA targets. Drive timing closure (setup/hold) across multi-mode/multi-corner (MMMC) scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform and/or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape-out execution (checklists, ECO flows, signoff r

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the team defining the future of memory systems. Our DRAM Architecture organization works at the intersection of silicon, packaging, systems, and customers to build technologies that power next-generation platforms. If you enjoy solving ambiguous problems that matter at industry scale, this is the place. This role is a senior technical leadership position with broad architectural ownership. You will develop complete DRAM system architectures, impact industry direction, and engage directly with customers and executives to convert complex ideas into scalable products. Responsibilities: Define next-generation memory system builds focusing on performance, capacity, RAS, and telemetry Lead cross-stack co-optimization spanning silicon, package, module, board, and system Architect sophisticated RAS and telemetry features and translate system needs into silicon Drive long-range memory technology strategy and influence industry standards Act as a senior technical liaison to customers, executives, and partners Minimum Qualifications: Bachelor’s degree or relevant equivalent experience in EE, CE, CS, or a related field Extensive hands-on experience in DRAM or memory systems architecture Deep understanding of DRAM timing, signaling, power, and reliability mechanisms Proven ability to translate system requirements into silicon architecture Preferred Qualifications: Master’s degree or PhD, or equivalent experience, in a related technical field Recognized techn

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Introduction: The Advanced Packaging Technology Development (APTD) team at Micron drives the technologies that enable the AI era. We work hands‑on with global R&D, suppliers, and manufacturing teams to turn breakthrough ideas into production‑ready solutions. Our work sits at the intersection of innovation, scale, and real‑world impact—and collaboration is how we win Position Overview: Artificial intelligence is transforming the world, and High Bandwidth Memory (HBM) is at the center of that transformation. As a Senior or Staff Engineer on the Dry Etch R&D team, you will play a key role in developing and scaling plasma‑based etch processes that enable next‑generation packaging technologies. This role offers deep technical ownership, broad cross‑functional collaboration, and the opportunity to influence long‑term technology roadmaps from early research through high‑volume manufacturing. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Are you eager to be a pioneer in AI and semiconductor breakthroughs? At Micron, we invite a passionate Staff Engineer, Collateral Integration Engineer to join our upbeat group. This opportunity offers the chance to work on innovative technology within a team-orie

At Kailera, we are bold, authentic and committed to our mission of developing therapies that give people the power to transform their lives and elevate their overall health. Rooted in an entrepreneurial spirit and a team-oriented culture, we are working together to advance Kailera’s mission to advance novel therapies for obesity and related conditions. We are passionate about creating an inclusive workplace that promotes collaboration, integrity, and excellence. As we expand, we seek the most talented individuals with diverse backgrounds, cultures, perspectives, and experiences to join our team. What You’ll Do: Reporting to the Chief Technology Officer (CTO), the Vice President (VP), Global Supply Chain will lead Kailera's end-to-end clinical and commercial supply chain, ensuring patients and clinical sites receive a reliable, uninterrupted supply of both Investigational Medicinal Product (IMP) and commercial drug product. This leader will set the global supply strategy, build and develop a high-performing team, and establish strong, well-governed partnerships with external service providers. Working closely with CMC, Clinical, Regulatory, Quality, Commercial, and Corporate functions, the VP will ensure supply plans meet global quality and regulatory standards and scale with the company's growth. As a senior member of the Technical Operations leadership team, this individual will partner with the CTO to shape and sustain a culture of collaboration, accountability, and operational excellence. Required location: Waltham, MA (hub-based, onsite 3-4 days per week) OR Remote (home-based, onsite at a hub 1 week every other month). Responsibilities: Recruit, develop, and retain a strong global supply chain organization. Establish clear governance structures and performance metrics for tracking and reporting Manage performance of external partners, including packaging and labeling vendors, third-party logistics providers (3PLs), and distributors, API and

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About the Role Micron's Market Intelligence team shapes how the company sees the memory market: where demand is heading, what is driving it, and how our competitors are positioning. We are looking for an analyst based in Taiwan who can act as our eyes and ears in the heart of the semiconductor supply chain. This role suits someone early in their career, likely coming from sell-side or buy-side equity research covering foundry, memory, or memory suppliers, who already has a strong network across the industry and a good instinct for where the market is moving. You will turn what you hear and observe into differentiated, ahead-of-consensus insight for our team. You will also take on core operating responsibilities: TAM reporting to cross functional teams, data center TAM alignment with cross functional teams, and supporting our internal planning system and data management work. What You Will Do Market and ecosystem intelligence Build and maintain a network across foundries, OSATs, hyperscaler supply chains, ODMs/OEMs, substrate and equipment suppliers, and the investment community in Taiwan and Korea. Spot early signals on industry direction, such as capacity moves, product transitions, build plans, and inventory and pricing behavior, so the team sees shifts before they show up in consensus or published reports. Track the ecosystem drivers of memory demand, including AI accelerator and GPU ramps, CoWoS and advanced packaging capacity, server builds (AI

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. As an Engineering Project Management Engineer in Advanced Packaging Technology Development at Micron Technology, Inc., you will be responsible for leading and managing Micron’s Advanced Packaging Technology Development projects. Your role will focus on overseeing technology development operations across various TD and pre-NPI projects, ensuring that results are delivered on time and in line with APTD’s technology roadmap and commitments. This position requires a customer-obsessed leader who will play a key role in the planning and implementation of APTD builds. You will engage with internal customers and both internal and external stakeholders, working collaboratively to ensure successful and timely project handovers. Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Project/Program Management: Lead technology development programs and projects to deliver against defined go-to-market timelines. Align program- and project-level plans, dependencies, and deliverables to ensure timely, c

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are part of Micron’s High Bandwidth Memory (HBM) Design Architecture organization, where we push the limits of memory technology every day. Our team works across global, multicultural engineering groups to build next-generation HBM solutions that power AI and machine learning. We believe the best ideas come from collaboration, curiosity, and a shared drive to innovate! This role plays a critical part in ensuring the reliability of Micron’s most advanced DRAM and HBM products. As an ESD & Latch Up Engineer, you will shape protection strategies from early design through high-volume manufacturing, working hands-on with silicon, layout, and foundry partners. If you enjoy solving deep technical problems and influencing product robustness at scale, this role offers both impact and growth. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define and own chip-level and IP-level ESD and latch up strategies for HBM DRAM, base die, I/O, TSVs, and die-to-die interfaces Establish ESD and latch up requirements, targets, and sign-off criteria aligned with JEDEC/ESDA standards Enable ESD protection circuits and latch up safe layout practices across designs and technologies Lead silicon validation, failure analysis, and correlation of pre-silicon assumptions to silicon results Act as the technical interface to foundries and partner closely with design, packaging, reliability, and product teams<

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The DRAM Architecture team is responsible for defining the system‑level and silicon‑level architectures that enable Micron’s memory products. The team works across technology generations and product lines, collaborating with design, product, systems, and ecosystem partners to deliver scalable, reliable, and high‑performance memory solutions aligned with customer and market needs. This role provides senior‑level architectural leadership to help shape Micron’s next‑generation DRAM products. As a Distinguished Member of Technical Staff, you will influence memory architecture decisions across semiconductor chips, assembly methods, component units, and system interfaces, contributing to both near‑term product execution and long‑term technology direction. This role requires AI proficiency or AI‑enabled ways of working. Responsibilities: • Define and evolve DRAM system architectures that address performance, capacity scaling, reliability (RAS), and observability requirements. • Collaborate across functions to evaluate architectural trade‑offs spanning DRAM silicon, packaging, modules, boards, and system platforms. • Influence host memory controller and platform architecture through technical engagement with CPU, GPU, and SoC partners. • Contribute to RAS and telemetry feature definition, translating system‑level needs into implementable architectural concepts. • Support exploration of emerging memory technologies and assess their impact on future product roadmaps. • Engage with cus

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions for AI, machine learning, and high-performance computing applications. We are seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. This role focuses on PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks that enable industry-leading bandwidth, power efficiency, and robustness. The successful candidate will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture teams to define architectural requirements, drive technology innovation, and ensure successful translation from concept to silicon. As a technical leader, you will influence future HBM roadmap decisions, develop engineering methodologies, and mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design. Key Responsibilities Define and drive next-generation HBM PHY and IO architecture , balancing performance, power, area, reliability, and manufacturability requirements. Architect high-performance transmit and receive paths , including clocking, signaling, equalization, timing alignment, and interface optimization. Define and optimize analog calibration architectures , including impedance calibration, reference v

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Staff DFT Design Engineer, you will work on design, simulation, and validation of next generation High Bandwidth Memory (HBM) architectures and circuit blocks. The HBM DFT Design Engineer is responsible for defining, designing, and integrating Design for Test (DFT) architectures for next generation High Bandwidth Memory (HBM) products. This role ensures robust test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost. The engineer works in a multi-functional manner with HBM build, verification, product engineering, test enablement, packaging, and external partners to deliver manufacturable, high quality HBM solutions. Responsibilities will include, but are not limited to: Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at‑speed test structures. Develop DFT solutions for both base die and DRAM die, considering stacked‑die and cube‑level test requirements. Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. Support yield learning, failure analysis, and debug by enabling observability and controllability in silicon. Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Product Development Team Leader (PDTL) for High Bandwidth Memory you will lead the introduction, ramp and high-volume production success of our groundbreaking products targeted to deliver lowest power per bit solutions in the field of ML(machine learning) and AI (artificial intelligence). PDTLs are the technical program owners and leaders, providing direction and leadership to cross-functional teams, including partners such as business units, quality, test, supply chain, packaging development and manufacturing. The success of a sophisticated product such as HBM relies vastly on PDTLs driving vertical integration of this wide network of partners across the company. This impactful role has a broad scope and will develop your skills working in an inclusive diverse environment of multicultural teams across worldwide geographies! Key Responsibilities include, but are not limited to: Technical Leadership : Lead HBM

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We work directly with the world’s leading system and platform companies to shape how memory technologies are used in real products. Our team sits at the intersection of customers, architecture, and engineering, turning sophisticated system challenges into actionable technical direction. If you enjoy deep technical problem-solving with real customer impact, this team delivers it every day! This role is central to our strategic customer partnerships. As part of Customer Technology & Solutions Architecture, you will lead hands-on technical engagements with key customers, help define solutions across memory, packaging, and systems, and ensure customer needs are clearly translated into internal product and technology decisions. You’ll operate with high ownership, strong technical credibility, and direct influence! Responsibilities: Serve as the primary technical interface for assigned strategic customers Engage customer architects and engineers across component, package, and system levels Define customer problems and co-develop cross-domain technical solutions Translate customer needs into clear inputs for product, architecture, and technology teams Act as ongoing technical owner for key accounts, supporting reviews, evaluations, and issue resolution Minimum Qualifications: Bachelor’s degree or equivalent practical experience in Electri