Advance Packaging Process Development Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. 1. Global Category Strategy & Market Leadership - Own and define global category strategies for Advanced Packaging Material to drive innovation in solutions for HBM and wafer-level packaging technology. - Lead market intelligence, including: Supplier landscape & capability mapping, Technology roadmaps & inflection points, Pricing models and long ‑ term cost curves. - Shape dual ‑ source / alternate ‑ source strategies and supply base optimization to mitigate concentration and continuity risks. 2. Executive ‑ Level Supplier Relationship Management - Act as Micron’s primary commercial lead for strategic material suppliers, executive reviews, and escalation governance with supplier executives. - Drive alignment on Capacity commitments, Technology enablement and Long ‑ term partnership frameworks. 3. Commercial Negotiation & Contracting - Lead sourcing events/RFQ process into bundled negotiation - Lead negotiations for contract extensions and renewals, renegotiation of prices, transfers, etc - Apply should ‑ cost, total cost of ownership (TCO), and global benchmarking models to negotiations. - Own strategy, governance, and renegotiations as market or capacity conditions shift. 4. Cost,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Mechanical Simulation Engineer, you will drive thermo-mechanical and multiphysics modeling for advanced semiconductor packaging technologies including HBM, 2.5D, and 3D integration. The role focuses on enabling robust package design through advanced simulation, material characterization, and failure mechanism understanding. You will actively integrate Generative AI, AI Assistant tools, and broader Artificial Intelligence capabilities to optimize modeling workflows, enhance predictive analytics, and automate complex simulations. This includes leveraging AI to improve simulation accuracy, reduce cycle time, and enable advanced modeling capabilities. You will collaborate with cross-functional teams across package architecture, fabrication, and assembly process integration to develop predictive simulation methodologies and influence design decisions. Job Responsibilities: Perform linear and non-linear static analysis for package and material behavior Conduct fatigue, fracture mechanics, and reliability simulations for advanced packages Develop multiphysics models (thermo-mechanical, therm

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description Summary: We are seeking an experienced Fail-Mode Metric Reaction (FMR) Engineer to drive yield analysis, failure mode characterization, and failure mechanisms understanding across test vehicles and advanced packaging products. This role owns the reaction loop between defect signatures observed in the line and the corrective actions taken by process, build, and reliability partners — spanning time-zero defects, internal reliability fails, and customer RMA returns! Job Description: Key Responsibilities: Perform yield analysis for advanced packaging test vehicles and production products, producing clear breakdowns of defect signatures by fail mode, location, layer, and process step. Investigate and root-cause fail modes and fail mechanisms at time-zero, correlating electrical signatures with physical failure analysis findings. Drive reaction plans on internal reliability fails and customer RMAs, translating failure mechanism understanding into containment, corrective, and preventive actions. Partner closely with: APTD Process teams — for process excursion triage and corrective action. APTD FA labs — for physical FA planning, sample prioritization, and interpretation. PSE (Product/Package Silicon Engineering) and TSE (Test/Silicon Engineering) teams — for test coverage, screen enhancement, and product-level dispositioning. Build and maintain data analysis pipelines, dashboards, and automated wor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities and Tasks: • Accountable and sustain for Bond process. • Backup for Debond area process basic maintenance. • Establish and improve process condition and technology. • Upgrade tool capability and improve product quality. • Establish and modify process management projects. • Set up process parameters for a variety of semiconductor equipment. • Evaluation, promotion and planning of new equipment / materials. • Abnormal analysis and improvement. • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization. Qualifications and Skills • Experience in wafer bonding, debonding, coating, lithography, thin film, or advanced packaging processes is preferred. ​ • Establish and improve process condition and technology.​ • Upgrade tool capability and improve product quality.​ • Establish and modify process management projects.​ • Set up process parameters for a variety of semiconductor equipment. ​• Evaluation, promotion and planning of new equipment / materials. ​• Abnormal analysis and improvement.​ • Leveraging AI and data analytics tools to enhance process monitoring, root cause analysis, predictive maintenance, and process optimization for semiconductor manufacturing operations. Requirement:​

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. • Identify, diagnose and resolve assembly process related problems • Coordinate and execute process, equipment and material evaluation / optimization initiatives and implement changes at process step • Lead / participate in continuous yield improvement and cost reduction activities • Validate and fan out new process baseline qualified, including new process, tools and/or materials for new product introduction • Support SPC/FDC/RMS/APC • Support site to site portability • Manage / audit material suppliers to achieve quality, cost and risk management objectives • Support internal and external audits Requirement: 1 years of experience in semiconductor manufacturing, packaging, or assembly processes. Ability to work in a cleanroom environment and flexibility to support on-call rotations or shifts when critical production issues arise. Strong analytical thinking, proactive problem-solving mindset, and a high degree of self-motivation. About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses infor

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Key Responsibilities Engineering Operations Support Create, release, and track engineering lots within manufacturing systems. Monitor hold lots and support timely issue resolution. Execute authorized MES transactions, including lot creation, issue lot, undo process, and lot recovery activities. Support CQ lot start requests and engineering build execution. Support engineering and manufacturing operational meetings and follow-up actions. Material & Logistics Management Receive FOUPs from warehouse and verify material readiness. Perform FOUP/FOSB transfers to support engineering and qualification activities. Execute FOSB packaging and shipment preparation. Prepare shipment documentation and logistics records. Coordinate wafer and sample delivery for laboratory analysis activities. Support kit and re-kit activities for engineering lots. Inspection & Process Support Configure inspection-related recipes and operational setup activities. Modify and maintain Atlas maps to support engineering execution. Support transaction recovery activities, including system troubleshooting and data verification. Perform routine operational checks to ensure lot readiness and processing continuity. Troubleshooting & Continuous Improvement Investigate hold lot issues and support recovery actions. Escalate manufacturing

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The PDE API Process Integration (PI) Engineer is responsible for driving process integration excellence for Advanced Packaging products, including High Bandwidth Memory (HBM) products across sites during New Product Introduction (NPI) . This role ensures robust process readiness, yield ramp, and cross‑module integration across Front-end to Assembly interactions , PWF, Assembly, and Test , enabling successful execution of HBM technology roadmaps. The PI Engineer works cross‑functionally with different cross-functional teams including Fab, Assembly, Test, Yield, Quality, and central engineering teams to identify risks early, resolve complex integration issues, and deliver NPI milestones on time. Job Responsibilities Technical Leadership Serve as the Process Integration Subject Matter Expert, owning end‑to‑end integration across PWF, assembly, and test from NPI through sustained HVM Define PI technical direction, integration frameworks, and success criteria for HBM programs Lead process characterization strategy, window definition, and systemic yield improvement Resolve complex yield, reliability, and performance issues through deep technical analysis and integration expertise Drive resolution of high‑impact, ambiguous, cross‑site integration challenges affecting ramp, quality, or business commitments Anticipate risks early and define mitigation strategies across programs and sites

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We are the team defining the future of packaging of complex memory systems! Our Package pathfinding and Architecture organization sits at the intersection of silicon, packaging, systems, and customer needs—turning complex scaling challenges into technologies that power next generation platforms, through cutting edge packaging technologies. If you enjoy working on problems with real industry impact, look no further! This is a technical pathfinding role driving forward-looking packaging technology for next generation memory systems from datacenter to edge-AI. You will leverage understanding of end to end memory system architectures, to guide long term package technology direction, and partner with customers, to build innovative ideas into scalable products. You will interface between package process technology, materials, electrical, thermo-mechanical and system performance areas to guide the package strategic roadmaps for Micron. Responsibilities: Define next‑generation package pathfinding and system architectures optimizing for speed performance, system bandwidth, power, capacity, thermal, mechanical and electrical performance. Lead cross‑stack co‑optimization across silicon, package, board, and system with package centric solutions approach Drive long‑term memory technology packaging strategy and influence industry standards Work closely with silicon, and system design teams and customers for next generation and long term disruptive solutions to boost speed performance for edge-AI and d

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Interested in changing the landscape of artificial intelligence workloads? Join our team where we are building next-generation, high-bandwidth memory products. In Micron's High Bandwidth Memory Architecture organization, we partner closely with customers to deliver memory solutions purpose-built for emerging AI systems and applications. As a Principal Layout Designer in the Next-generation HBM Architecture Team , you will drive layout for 3D-stacked, high-performance memories. Apply your knowledge to deliver high-quality layout designs across analog and/or mixed-signal domains in collaboration with peer architecture, design, and packaging teams. Implement layout designs for early architecture concepts to demonstrate feasibility and identify optimizations. Responsibilities: Design layouts for critical analog and mixed-signal blocks. Drive exploratory layout process for next-generation architectures, including floorplanning, placement, and routing. Integrate full chip designs and perform layout verification (LVS, DRC), quality checks, and documentation. Collaborate and communicate across domains, including signal integrity, architecture, design, and advanced packaging, to ensure successful architecture exploration. Minimum Qualifications: Hands-on layout experience with critical analog blocks and full designs. Experience with Cadence VLE/VXL and Mentor Graphics Calibre DR

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: • Own and deliver critical HBM IO blocks and subsystems from architectural definition through circuit and RTL implementation, verification, tape-out, silicon bring-up, and post-silicon debug, including interfaces supporting future CPO systems. • Define HBM PHY, controller-to-PHY, die-to-die, clocking, training, calibration, power-management, error-handling, and test requirements for advanced heterogeneous systems. • Drive robust, high-performance builds by balancing bandwidth, latency, power, area, reliability, electrical signal quality, power stability, yield, and manufacturability trade-offs. • Lead architecture and design of analog, mixed-signal, and digital interface functions used in high-speed memory subsystems. • Partner with package, interposer, physical design, signal integrity, power integrity, and thermal teams to optimize interface implementation across 2.5D and 3D systems. • Lead root-cause analysis and resolution of complex pre-silicon and post-silicon issues across circuit design, RTL, architecture, process, package, interposer, and system interactions. • Serve as technical project lead for one or more advanced interface programs, coordinating execution across architecture, design, layout, verification, validation, packaging, test, and product engineering teams. • Define and communicate technical priorities, interface specifications, execution plans, risks, dependencies, and schedule impacts. • Work with internal teams, customers, IP pr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. DRAM ASIC Architecture Role Overview Micron is seeking an experienced architect to drive the definition of next-generation DRAM products incorporating advanced CMOS-based logic die technologies. This role will help define how future DRAM products leverage advanced CMOS logic die technologies to enable higher levels of integration, observability, reliability, power efficiency, security, and system differentiation beyond what is achievable in conventional DRAM-only implementations. The architect will define architectures that leverage advanced logic die capabilities to complement and enhance DRAM functionality across LPDDR, DDR, HBM and future heterogeneous memory solutions. The successful candidate will architect I/O, reliability, manageability, interface, test and system-enhancement functions. The role requires strong collaboration across DRAM design, ASIC architecture, packaging, process technology, product engineering, validation, firmware, and system architecture teams. Key Responsibilities Define next-generation DRAM + logic-die architectures, including functional partitioning between DRAM arrays, peripheral circuitry, and advanced CMOS logic die platforms – to optimize performance, power, cost, reliability, and product differentiation. Identify and evaluate system, interface, reliability, test, management, and control functions that may benefit from advanced logic-die implementations; perform architectural tradeoff analysis coverin

ADVANCED PACKAGING TD - SR ENGINEER PROCESS INTEGRATION — Taichung - Fab 16, Taiwan. Apply via Workday.

Principal Wet Process Engineer, Advanced Packaging — Boise, ID - Main Site. Apply via Workday.

Staff Process Engineer, Advanced Packaging CMP — Boise, ID - Main Site. Apply via Workday.

Principal/Staff, APTD - Advanced Packaging Wafer Level Technology Process Engineer — Fab 10A, Singapore. Apply via Workday.