Advance Packaging Process Development Engineer Jobs

We’re looking for a hands-on process and materials engineer to own wafer level molding and underfill processes, material qualification, and assembly integration across development and manufacturing. Summary: Seeking an experienced engineer to lead wafer level mold and underfill process development for advanced semiconductor packages (fan-out wafer level packaging, 2.5D/3D, chiplet). This role spans mold compound and underfill material selection and qualification, wafer level molding and encapsulation processes, underfill dispense and cure, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize wafer level molding processes including compression molding, transfer molding, and mold underfill (MUF) for fan-out and advanced heterogeneous packages. Own mold compound and underfill material selection and qualification, including evaluation of filler content, CTE, modulus, Tg, viscosity, and moisture uptake to meet thermo-mechanical and reliability requirements. Drive underfill process development including capillary underfill (CUF) dispense strategies, flow and void optimization, and cure profile development for high-density flip chip and chiplet assemblies. Evaluate and mitigate assembly risks including warpage, delamination, void formation, bleed-out, mold flash, and filler settling; define process windows and controls to ensure repeatable yield across wafer and panel formats. Collaborate with OSATs and material suppliers to qualify mold and underfill materials, define dispense and cure equipment requirements, and manage process transfers into production. Lead characterization of mold and underfill material properties (viscosity, gel time, cure kinetics, adhesion, CTE, modulus) and correlate material behavior to process outcomes and package reliability. Work closely with thermal mechanical modeling teams to model solder joint reliability of bump interconnects with va

We're seeking experienced engineers to contribute to flip chip package development and assembly processes for advanced semiconductor devices (2.5D/3D/chiplet/fan-out/flip-chip). This spans bump metallurgy, substrate integration, reflow and underfill processes, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities: Develop and optimize flip chip attach processes including bump formation, placement, reflow, and underfill for high-performance semiconductor packages. Define and manage bump metallurgy stacks (e.g., Cu pillar, SnAg, micro-bumps) and substrate pad finishes for robust interconnect performance. Drive package integration from die to substrate, ensuring alignment, coplanarity, and yield optimization. Evaluate and mitigate assembly risks including warpage, non-wet opens, voiding, head-in-pillow, and interconnect defects. Collaborate with substrate vendors, OSATs, and internal teams to define design rules (pad pitch, bump pitch, keep-outs, stack-ups). Lead process development for reflow profiles, flux selection, cleaning, and underfill dispense/cure. Perform root cause analysis of assembly and reliability failures using cross- sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manufacturing teams to ensure robust package performance from concept through high-volume production. Required Technical Skills: Strong experience in flip chip packaging and assembly processes for semiconductor devices. Deep understanding of bumping technologies (solder bumps, Cu pillar, micro- bumps) and UBM/metallization systems. Experience with underfill materials, dispense techniques, flow behavior, and cure processes. Understanding of thermo-mechanical behavior in flip chip assemblies (CTE mismatch, warpage, solder

We’re seeking an experienced engineer to lead bump interconnect development for advanced semiconductor devices (2.5D/3D/chiplet/fan-out). This role spans ubump and C4 bump metallurgy, RDL design and plating, chip-side and interposer capture pad design rules, OSAT engagement, reliability, failure analysis, and cross-functional support through package and system productization. Core Responsibilities Own end-to-end bump interconnect development for both ubump (micro-bump) and C4 processes, including bump formation, and reflow for use with mass reflow, TCB, and LAB chip attach for high-performance semiconductor packages. Define and own bump metallurgy stacks for ubump (e.g., Cu pillar/SnAg) and C4 (e.g., SAC alloys) interconnects, including UBM selection and pad finish specifications for both chip-side and interposer capture pads. Develop and own design rules for bump interconnects including pitch, bump diameter, standoff height, keep-outs, and land pad geometry for both the chip side and interposer or substrate capture pads. Lead RDL (redistribution layer) process development including electroplating of Cu RDL traces, via fills, and pad finishes; define RDL design rules for line/space, via diameter, and layer stack-up to meet electrical and reliability requirements. Collaborate with OSATs and bumping foundries to qualify ubump and C4 bumping processes, drive design rule alignment, and manage process transfers into production. Evaluate and mitigate bump interconnect assembly risks including non-wet opens, voiding, head- in-pillow, intermetallic growth, and joint fatigue failures across both ubump and C4 interconnect types. Perform root cause analysis of assembly and reliability failures using cross-sectioning, SEM, CSAM, and other failure analysis techniques. Support reliability qualification including thermal cycling, drop, mechanical shock, and power cycling. Work cross-functionally with design, reliability, thermal, and manu

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Overview As a Staff/Senior Process Development Engineer within PDE-CEM, you will leverage advanced semiconductor process characterization, failure analysis, yield analytics, and process integration expertise to accelerate product and technology development. The role focuses on developing robust assembly processes, improving yield and reliability, supporting New Product Introduction (NPI), and utilizing data-driven methodologies to optimize manufacturing performance. The ideal candidate combines strong semiconductor physics knowledge, advanced characterization skills, yield improvement experience, and cross-functional leadership capability to drive continuous process innovation and manufacturing excellence. Key Responsibilities Process Development & Characterization Develop and optimize Process of Record (POR) for assembly and packaging technologies. Establish process windows, process capability targets, and characterization strategies. Apply statistical methodologies including DOE, SPC, JMP, and Six Sigma to characterize and optimize manufacturing processes. Drive early process learning through advanced characterization and failure analysis techniques. Yield Improvement & Problem Solving</

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary: As an Advanced Packaging Characterization Engineer within Advanced Packaging Technology Development (APTD), your responsibilities include but are not limited to providing package development characterization and failure analysis support for development test vehicles, qualifications, customer returns, new product introduction, and general test failures. You are the domain expert on advanced packaging characterization methodology and responsible for establishing relevant analysis methods needed to support technology development. You will also have a thorough understanding of product package assembly and process flow, to work with Process Integration, Process Development, and Product Engineering groups ensuring failures are classified and root cause fixes implemented. Main Responsibilities: Conduct Electrical and PFA Characterization Perform electrical fault analysis to pin-point hot

Job Details: Job Description: As one of the world's largest semiconductor manufacturers, Intel is committed to advancing every aspect of semiconductor technology, from process development and manufacturing to advanced packaging and reliability characterization. Employees within Intel Foundry are part of a global network spanning technology development, manufacturing, assembly, test, and quality organizations across both front-end silicon and advanced packaging facilities. You will join the Foundry Lab Network (FLN), a key organization within Foundry Quality, Reliability, and Labs (FQRL), located at Intel's growing Chandler, Arizona site. This site serves as the technology development hub for Intel's most advanced packaging technologies, including Hybrid Bond Interconnect (HBI), Embedded Multi-die Interconnect Bridge (EMIB-T), glass substrates, Foveros, and future advanced packaging innovations. FLN is actively expanding its laboratory capabilities and capacity to support Intel Foundry's roadmap, enabling faster technology qualification and accelerating development cycles through Quick Turn Monitoring (QTM) solutions that significantly reduce time-to-data. As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within FLN. You will partner closely with Packaging Technology Development, Quality and Reliability, and Failure Analysis teams to establish and enhance laboratory capabilities that support qualification and certification of next-generation packaging technologies and products. This position offers a unique combination of people leadership, technical problem solving, and organizational strategy. You will lead a team of 7-10 talented engineers, spearhead cross-functional efforts to resolve complex reliability and technology challenges, drive strong quality and operati

Job Details: Job Description: The Role and Impact We are seeking a Silicon Packaging Design Architect to join our team, where you will drive end-to-end package solutions for physical, electrical, and cost requirements. In this senior engineering role, you will collaborate with cross-functional teams to design, troubleshoot, and continuously improve packaging standards and processes, ensuring high-quality package output. Your contributions will directly impact the seamless transition of designs to production and enhance Intel's advanced packaging technologies. Business Group As part of Intel Corporation's dynamic and innovative ecosystem, this role resides within the Silicon Packaging Architecture team, focused on developing advanced packaging solutions that enable Intel's cutting-edge silicon technologies. The team plays a vital role in ensuring packaging, and 3D IC designs meet technical, mechanical, and reliability standards while supporting Intel's broader mission to drive world-changing advancements in technology. Key Responsibilities Translate product requirements into detailed package architecture specifications. Drive technology tradeoff decisions to ensure silicon packages conform to electrical, mechanical, thermal, and reliability standards. Collaborate with silicon, hardware, and package teams to deliver high-quality package solutions and overcome roadblocks. Oversee the end-to-end package development process, including design, procedures, and continuous improvements to quality standards. Troubleshoot packaging designs and resolve issues related to materials and processes, providing innovative and cost-effective solutions. Implement co-design strategies between silicon and board design teams to optimize product

Shift Process Engineer, Advanced Packaging Technology Development (APTD) — Boise, ID - Main Site. Apply via Workday.

Shift Process Engineer, Advanced Packaging Technology Development (APTD) — Boise, ID - Main Site. Apply via Workday.

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Role Summary: We are currently experiencing a ground-breaking period in artificial intelligence (AI), where AI is anticipated to become an integral component of daily life. This proliferation is being fueled by advances in memory and compute technologies. High bandwidth memory (HBM) is at the forefront of these innovations. Micron’s Advanced Packaging Technology Development (APTD) is responsible to deliver package development for high performance memory products and transfer to manufacturing. Your responsibilities include but are not limited to developing and enabling deployment of processes related to the post-fab wafer finishing processes in semiconductor manufacturing to meet performance, cost, manufacturability, quality, reliability and schedule requirements. You will have opportunity to work with peers and partners across organizations to coordinate the development and launch of new technologies and integration flows for solutions that drive the future. Main Responsibilities: Process Development: Establish and improve process management projects to deliver technology node requirements and scaling for next node for wafer level process conditions and technologies including photolithography, dry etch, CMP, wet process, de

Job Details: Job Description: The Advanced Packaging Technology Development (APTD) Substrate and Wafer Assembly organization is responsible for developing cutting edge substrate packaging and wafer assembly solutions for our customers. As a member of the Substrate Technology and Manufacturing Group, you will play a critical role in enabling new manufacturing capacity across advanced packaging suppliers. In this position, you will lead substrate supplier development and qualification activities for advanced technologies such as high density FCBGA, EMIB-T and glass core substrate, ensuring suppliers achieve the required readiness to support growing customer demand. This includes driving technical enablement, managing readiness milestones, and collaborating closely with cross functional engineering teams and supplier partners. A combination of detail-oriented project management, strong technical risk assessment / problem solving skills, and effective supplier / stakeholder management will be needed to be successful. Please note: This role requires periodic evening meetings with suppliers in East Asia, as well as occasional travel to supplier sites to support essential program objectives. Key Responsibilities Define process integration roadmaps and establish manufacturing procedures to meet technology transfer milestones. Extract insights from structured and unstructured data, applying statistical analysis and coding techniques for yield improvement. Lead low yield analysis and corrective actions to address quality excursions in high-volume production environments. Drive continuous improvement initiatives to minimize defects and optimize process reliability. Assess quality and reliability risks for manufacturing material and process changes, ensuring sustained product performance. C

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Job Description Position Summary As an IoT Engineer, Engineer based in Singapore, you will design, build, and deploy Industrial IoT (IIoT) and machine vision solutions to support advanced packaging technology development and factory enablement. You will implement hands-on engineering work from proof-of-concept through deployment and sustainment, contributing to scalable and secure solutions that improve quality, productivity, and early risk detection. You will collaborate cross-functionally to translate manufacturing needs into measurable signals, robust data pipelines, and actionable insights, while operating with a strong safety mentality and a bias for practical, reliable delivery. Key Responsibilities Develop and deploy IIoT solutions end-to-end: sensing strategy, edge compute, connectivity, data ingestion/storage, monitoring, and sustainment (including data quality and traceability). Build machine vision solutions: support hardware selection (cameras/optics/lighting), image acquisition strategy, algorithm development, performance validation, and deployment readiness. Work with process, equipment, automation, quality, and IT/data platfor

Job Details: Job Description: Join Intel's Advanced Packaging Technology Development - Substrate and Wafer Assembly (ATPD: SWA) team and help us fulfill our mission to be the supplier of choice for leading-edge, cost-effective substrate packaging. As a Manufacturing Equipment Technician, you will support critical manufacturing equipment and drive continuous improvement in a highly technical, cleanroom production environment. Shift 5: Shift 5: (days frontend) AM-PM Sun-Tues and alternating Wednesday days / Hours: 6:00 a.m.-6:00 p.m. Manufacturing Equipment Technicians in Advanced Packaging Technology Development: Substrate and Wafer Assembly are responsible for: Performing electrical and/or mechanical troubleshooting to diagnose issues with non-functioning electromechanical equipment used in semiconductor manufacturing. Dismantling, adjusting, repairing, and assembling equipment according to layout plans, blueprints, operating or repair manuals, rough sketches, or engineering drawings. Performing setup, calibration, and preventive maintenance on production equipment, with a focus on wet chemistry, plating, and dry high-vacuum toolsets. Documenting maintenance activities, repairs, parts usage, and findings in accordance with established procedures and systems. Collaborating with engineering, process, and support teams to improve tool performance, reduce equipment downtime, and enhance process capability and reliability. Leading or contributing to continuous improvement projects, including root cause analysis, yield and uptime improvement initiatives, and optimization of maintenance practices. Assignments are semi-routine in nature and performed within generally defined parameters. Employees normally receive general instructions on most work and are expected to exer

Silicon Product Integration Description - Role Overview We are seeking an experienced Product Engineer to lead silicon product engineering, foundry engagement, and NPI execution for next-generation MEMS programs. The role serves as the technical bridge between HP, foundry partners, design teams, manufacturing organizations, and worldwide program teams to ensure successful technology development, qualification, and high-volume manufacturing readiness. The successful candidate will combine deep semiconductor foundry experience with strong program leadership skills to drive product execution from technology development through qualification and production launch. Key Responsibilities Product Engineering Leadership Own silicon product engineering activities across development, qualification, ramp, and sustaining phases. Drive structural cost saving initiative in wafer Foundry and advanced packaging factories. Lead NPI silicon builds and ensure timely execution of wafer, and advanced packaging factories deliverables. Partner with design, architecture, reliability, systems, and manufacturing teams to close technical issues. Drive issue resolution and technical solution for the process marginality and escalation. Foundry and Technology Development Serve as the primary technical interface with internal/external foundries and technology partners. Drive technical reviews, process optimization, design enablement, and qualification activities. Lead root-cause investigations and corrective actions related to yield, reliability, and manufacturability. Assess technology options and recommend development strategies for future products. Program and NPI Leadership Program Management Leadership cross-functional execution for strateg

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Material Characterization & Analysis Perform material characterization using DSC, TGA, DMA, TMA, Rheometer, Contact Angle, Density, and other analytical techniques. Evaluate critical material properties including Tg, CTE, viscosity, modulus, cure behavior, filler content, thermal stability, and wettability. Analyze material behavior and establish correlations between material properties and manufacturing performance. Support incoming material evaluation, qualification, and supplier material assessments. Testing Method Development Develop, optimize, and standardize material characterization methods and testing procedures. Establish SOPs, OCAPs, SPC baselines, and MSA plans for laboratory operations. Develop new characterization capabilities for molding compounds, NCF, dicing tapes, liquid EMC, adhesives, and other packaging materials. Execute method validation, correlation studies, and cross-site benchmarking activities. Supplier Quality & Material Investigation Lead supplier material investigations for excursions, abnormal trends, and quality concerns. Conduct root cause analysis and drive corrective and preventive actions with suppliers. Support supplier audits, change management reviews, and material control plan optimization. Establish critical-to-quality (CTQ) monitoring strategies and strengthen supplier process control systems. Failure Analysis &