Architect Memory Subsystem Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Systems Software Engineer in the Storage and Memory Systems (SMS) group within Micron’s ITP Pathfinding organization, you will architect, design, and develop software that enables and demonstrates the value of future memory and storage technologies. You will work in a small, highly skilled engineering team, collaborating closely with AI/ML application and modeling specialists, software engineers, hardware engineers, and system architects. Your pathfinding work will accelerate the development of future products and influence technical direction. This role requires broad technical expertise and a willingness to contribute across multiple layers of AI and systems software stacks, from AI applications to hardware/software interfaces. Responsibilities Design and modify AI inference software stacks to enable proof-of-concept hardware capabilities. Develop software to quantify and demonstrate the value of proposed system features. Lead software architecture and development efforts, both independently and as a technical lead for small teams. Research emerging AI software topics to identify memory and storage system challenges and opportunities. Develop and modify Linux applications and libraries using C, C++, Python, Rust, CUDA, and/or SYCL for advanced heterogeneous computing systems. Develop and use emulators to predict system‑level performance and functional impacts in advance of hardware availability. Debug system-level issues spanning applications, libraries, o

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a System Architect at Micron Technology, Inc. you will be responsible for defining next generation of Managed NAND architecture, studying and reverse engineering system software and system hardware. Through the design/integration team you will provide support regarding MNAND products like eMMC and UFS, in Android/Linux platforms to: Characterize usage models and platform behaviors , Propose new ASIC architectures, FW models, NAND changes , Support BU’s customer discussion on next generation topics , AI impact on storage products . The ideal candidate for this role would share our passion for new topics, idea generation and prototypization , system modeling . Another important requirement is usage of AI tools for SW development: the candidate should be AI proficient in programming leveraging AI coding capabilities as well. We are looking for highly talented , passionate, and versatile engineer that can contr

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Principal Security Firmware Engineer on Micron's enterprise SSD team, you will design and develop security features that protect next-generation storage products against evolving cybersecurity threats. You will architect and implement cryptography-based solutions — including data encryption, Root of Trust, Secure Boot, Device Attestation, and Self-Encrypting Devices (SED) — while leading the transition to post-quantum cryptography for future product generations. This role spans the full Security Development Lifecycle, from threat modeling and architecture through implementation, testing, and certification. You will work across SoC, FPGA, and simulation platforms and collaborate cross-functionally to deliver security solutions aligned with industry standards including OCP, TCG, NVMe, and PCIe. Responsibilities Design and develop security features for Micron enterprise SSDs, protecting against cybersecurity threats across the product lifecycle Architect, implement, and debug cryptography-based security solutions including data encryption, Root of Trust, Secure Boot and Update, Device Attestation, and Self-Encrypting Devices (SED) Lead the transition to post-quantum cryptography algorithms (LMS, ML-DSA, ML-KEM) for next-generation products Implement security protocols aligned with OCP, TCG, NVMe, and PCIe specifications Debug security firmware on SoC, FPGA, and simulation platforms using tools such as JTAG, memory dumps, and bus analyzers Dri

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Country HR Director, Malaysia is a senior strategic leadership role responsible for leading the People function at country level and serving as the primary architect of people strategies aligned with business imperatives. The role localizes enterprise People strategies to strengthen talent, organizational agility, inclusion and a high-performance culture. As an AI-enabled People leader, the role also shapes responsible adoption of artificial intelligence across the People function, builds workforce readiness for AI-driven change, and combines human judgment with trusted data and digital insights to improve decisions, employee experience and operating effectiveness. Key Responsibilities Strategic Leadership & Business Partnership Define and champion a forward-looking People vision aligned with executive leadership, enterprise priorities and Malaysia business needs. Translate enterprise People strategies into country-specific initiatives that accelerate business outcomes and strengthen organizational resilience. Advise senior leaders on talent, capability and organization strategies that enable transformation, innovation and growth. Use workforce data, external intelligence and scenario-based insights to anticipate trends, assess organizational health and guide strategic choices. Serve as a trusted advisor and cultural steward, reinforcing Micron values and leading change with integrity. People Strate

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description The HBM Architecture team develops advanced datapath solutions that enable industry‑leading bandwidth, power efficiency, reliability, and scalability for Micron’s next‑generation High Bandwidth Memory (HBM) products. The team collaborates closely across design, PHY, ECC, verification, layout, and system groups to drive innovative logic‑die and core‑die architectures from concept through production. We are seeking a highly motivated HBM Datapath Architect to architect, design, and optimize high‑speed data paths for next‑generation High Bandwidth Memory (HBM) products! This role focuses on logic‑die and core‑die datapath circuitry, enabling industry‑leading bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. The ideal candidate will work closely with design, PHY, ECC, verification, layout, and system teams to deliver robust datapath designs from concept through silicon bring‑up and production. Responsibilities will include, but are not limited to: Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic Develop high‑speed, low‑latency datapath circuits supporting multi‑channel HBM architectures and wide internal buses Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Lead DFT Engineer Job Description: Developing silicon for edge-to-cloud computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities: Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements: Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Bachelor’s degree in a related field. Tools:

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron's Firmware & Product Test (FPT) team is hiring a Staff Engineer to lead validation strategy for enterprise SSD firmware. In this role, you'll architect next-generation test frameworks, drive AI/ML-powered validation methodologies, and own end-to-end verification of complex NVMe front-end features across multiple product lines. You'll serve as a technical authority at the intersection of firmware validation and applied machine learning — shaping the strategic direction of our test infrastructure, mentoring engineers, and influencing firmware architecture decisions through deep validation insights. The FPT team builds verification plans in Python, enforces NVMe and security protocol compliance, and executes white-box, grey-box, and black-box testing across simulation, FPGA, and prototype hardware environments. Responsibilities Lead the design and execution of firmware verification strategies for customer specifications and NVMe protocols, owning validation of complex front-end features (SMART, Trim, Get Log Page, OCP) across multiple product lines. Architect scalable grey-box, white-box, and black-box test frameworks that become organizational standards for firmware quality. Drive root-cause analysis for critical field and regression failures; establish systematic debug methodologies and knowledge-sharing practices across the team. Own the test infrastructure roadmap — including automation frameworks, CI/CD integration, and reporting dashboards — and influence t

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We define ESD and latch-up architecture for next-generation HBM products across advanced nodes and 3D integration. Our team works across device, circuit, and packaging domains to solve reliability challenges that directly impact product quality. We take on complex problems and turn them into scalable solutions that enable high-performance memory! As an SMTS/DMTS HBM ESD/Latch-Up Architect, you will define protection strategies across base die, DRAM stacks, and interconnects. This role shapes product reliability from early architecture through silicon validation. You will work across teams and influence technical direction while solving system-level ESD challenges. This role supports the design and deployment of AI-enabled solutions that improve efficiency and decision-making. Responsibilities: Define end-to-end ESD and latch-up architecture across base die, DRAM die, and interconnects Develop protection strategies for high-speed I/O, TSV interfaces, and advanced packaging Establish ESD/LUP standards, rule decks, and signoff criteria Drive correlation between d

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Staff Engineer: STA Methodology & Sign-off Lead We are seeking a high-caliber Staff or Senior Staff Engineer to architect and lead our SOC Static Timing Analysis (STA) Methodology along with execution responsibilities to eliminate the bottle-necks in STA and build bridges. This is a critical role for a forward-thinking engineer who excels at defining the frameworks and flows required to navigate the complexities of modern, large-scale SOC designs. Engineer will have scope to bridge Architecture, CAD, RTL, and Physical Design to establish a predictable, high-performance, and scalable path to tape-out. The Role As the lead for STA Methodology, you will own the sign-off architecture and the timing convergence strategy. Rather than just executing runs, you will build the "engine" that enables execution—defining flows, qualifying tools, establishing margin strategies (AOCV/LVF/POCV), and driving cross-functional alignment to meet aggressive Power, Performance, and Area (PPA) targets. Key Responsibilities Sign-off Methodology & Architecture: Define and own full-chip SOC timing sign-off criteria, including Multi-Mode Multi-Corner (MMMC) definitions, derate strategies, and operating condition mapping for functional, shift, and capture modes. Flow Development & Left-Shift Automation: Architect, deploy, and maintain adva

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators. Responsibilities Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization. Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges. Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations. Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR). Implement parsing, semantic analysis, and IR generation for deep learning frameworks. Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers. Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations. Qual

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. Job Description : Lead DFT Engineer (Edge Computing) Developing silicon for Edge Computing isn't just about speed; it’s about balancing high-performance data processing with extreme power efficiency and reliability in remote environments. As the Design for Test (DFT) Lead, you will be the architect of our testing strategy, ensuring our data center chips are flawlessly manufacturable and resilient enough for edge deployment. Key Responsibilities Architectural Leadership: Define and implement the end-to-end DFT architecture for complex SoCs, including Hierarchical DFT, Scan compression, Boundary Scan and MBIST. Edge-Specific Reliability: Develop strategies for In-System Test (IST) and power-on self-test (POST) to ensure chip health in remote edge data centers. Implementation & Flow: Oversee scan insertion, ATPG (Stuck-at, Transition, Path Delay), and Memory /Logic BIST. Cross-Functional Synergy: Collaborate with Design, Physical Design, and Yield teams to ensure high test coverage while minimizing area overhead and power impact as well as timing analysis . Post-Silicon Validation: Lead the bring-up and debug phase on ATE (Automated Test Equipment) to root-cause silicon failures and optimize test time. Technical Requirements Experience: 12+ years in DFT, with at least 2 years in a leadership or principal role. Tools: Mastery of industry-standard

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems. About the Role EnCharge AI is seeking a highly skilled and experienced AI Compiler Engineer to spearhead the efforts in developing and optimizing graph compilers tailored to cutting-edge AI and ML workloads. You will collaborate with hardware architects, and AI researchers to enhance performance, optimize computation graphs, and enable efficient model deployment on EnCharge’s Inference Accelerators. Responsibilities Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization. Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges. Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations. Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR). Implement parsing, semantic analysis, and IR generation for deep learning frameworks. Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers. Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations. Qual

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Micron is seeking an experienced NAND Storage Architect, Strategist, and Product Manager to drive, define and implement next-generation NAND technologies and methods for managing stored data in client SSDs. We bring together technical expertise, market insight, and cross-functional partnership to develop products that advance how the world uses information. Join us and influence the future of NAND storage! In this role, you will connect NAND architecture with business priorities, customer requirements, and market opportunities. You will work across Product Management, System Architecture, Engineering, Marketing, Operations, OEMs, and industry partners to develop differentiated storage solutions. Key Responsibilities Define NAND architecture, technology-node, and storage-solution strategies aligned with Micron’s business goals. Develop NAND storage requirements, including performance, reliability, power, packaging, cost, and system-level capabilities. Lead NAND roadmap planning from concept through product lifecycle achievements, using market trends, customer insights, and AI-workload requirements to guide decisions. Own NAND Storage Marketing Requirements Documents and support Technical Requirements Document development. Translate OEM, ecosystem, and business needs into clear product requirements and actionable technology plans. Evaluate NAND industry trends, competitor roadmaps, architectures, and emerging technologies to see opportunities for differentiation. En

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About our Team: Micron’s Industrial and Physical AI team is driving the transformation of semiconductor manufacturing through Autonomous Operations, AI, robotics, and digital twin technologies! We develop and deploy innovative solutions across Micron’s global fabrication and assembly/test facilities, enabling smarter, safer, and more efficient operations at scale. Position Overview: We are seeking a hands-on Full-Stack AI Engineer to design, build, and deploy production-grade AI applications that support Micron's Autonomous Operations initiatives. This role owns the end-to-end development lifecycle, from data pipelines and AI models to APIs, web applications, digital twin integrations, and cloud/edge deployments, delivering impactful solutions for engineers, operators, and business leaders worldwide. Responsibilities: Design, architect, and deliver end-to-end AI products, including data ingestion pipelines, feature engineering, model training/inference, APIs, user interfaces, and application monitoring. Build and maintain modern front-end applications using React, Angular, or Streamlit, supported by backend services in Python and Fast

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. About our Team: Micron’s Industrial and Physical AI team is driving the transformation of semiconductor manufacturing through Autonomous Operations, AI, robotics, and digital twin technologies! We develop and deploy innovative solutions across Micron’s global fabrication and assembly/test facilities, enabling smarter, safer, and more efficient operations at scale. Position Overview: We are seeking a hands-on Full-Stack AI Engineer to design, build, and deploy production-grade AI applications that support Micron's Autonomous Operations initiatives. This role owns the end-to-end development lifecycle, from data pipelines and AI models to APIs, web applications, digital twin integrations, and cloud/edge deployments, delivering impactful solutions for engineers, operators, and business leaders worldwide. Responsibilities: Design, architect, and deliver end-to-end AI products, including data ingestion pipelines, feature engineering, model training/inference, APIs, user interfaces, and application monitoring. Build and maintain modern front-end applications using React, Angular, or Streamlit, supported by backend services in Python and FastAPI. Develop scalable integrations between manufacturing systems, robotics platforms, AMRs, sensor networks, and enterprise applications to enable intelligent factory operations. Design and implement digital twin environments using platforms such as NVIDIA Omniverse, Gazebo, or Unity Robotics Hub to support simulation, validation, and o