Data Center Rack Integration Manager Jobs

About the Team The compute infrastructure team runs the GPU fleet and large-scale compute clusters that serve the models backing ChatGPT and the API, while also supporting training workloads for our next generation models. We operate a large, modern GPU fleet and provide a unified platform for other OpenAI teams to seamlessly run production Applied AI and Research training workloads. We seek to learn from deployment and distribute the benefits of AI, while ensuring that this powerful tool is used responsibly and safely. Safety is more important to us than unfettered growth. About the Role You’ll own the hands-on and automation work that brings WAN, fiber, carrier, and cloud-interconnect circuits into service. Partner with network engineers, fiber providers, cloud service providers, colocation teams, and data-center technicians to move each connection from ordered and patched to verified, stable, and ready for handoff. You’ll own Layer 1 troubleshooting and circuit bring-up while building workflows that translate reliable system or model output into precise, approved technician actions, capture field feedback, and drive each connection to a green-port handoff. The right person combines strong physical-networking judgment with practical automation skills: patch-panel and port mappings, optics and light levels, provider coordination, structured operational data, API or scripting workflows, and human-in-the-loop LLM tooling. Responsibilities Own Layer 1 activation and restoration for carrier circuits, dark fiber, wavelengths, Ethernet handoffs, and dedicated cloud interconnects across data centers and points of presence. Reconcile complete A-side/Z-side as-builts: circuit IDs, LOAs/CFAs, carrier demarcations, MMR/ODF/MDF and patch-panel positions, fiber pairs, cross-connects, optics, and device ports. Investigate no-light, low-light, wrong-port, link-flap, and error-rate issues across providers and CSPs; isolate continuity, dirty connectors, polarity, incorrect patching

About the Team The Finance Platform & Technology team at OpenAI builds and scales the future-proof systems and data architecture that power our core financial operations. We enable business agility, compliance, and operational excellence across quote-to-cash, procure-to-pay, inventory, and asset management for both B2B and B2C. Our focus is on modernizing workflows through strategic integrations, scalable automation, and seamless data flows empowering smarter decisions, reliable reporting, and sustainable growth as OpenAI evolves About the Role We are looking for a Supply Chain Transformation Architect to redesign and modernize our end-to-end supply chain operations supporting robotics, consumer hardware, and data center infrastructure. This role sits at the intersection of process, systems, and data. Your primary focus will be transforming supply chain processes across planning, procurement, manufacturing, logistics, and fulfillment—then enabling those processes with the right systems architecture, data foundation, and AI-driven automation. You will help move the organization from manual, reactive operations to intelligent, data-driven supply chain execution. In this role you will: Lead End-to-End Supply Chain Transformation Evaluate and redesign core supply chain processes across demand planning, supply planning, procurement, manufacturing operations, logistics, and fulfillment. Identify operational bottlenecks, fragmented workflows, and manual processes that limit scalability. Build standardized process frameworks and operating models that support rapid scaling of hardware programs. Drive Operational Excellence Implement structured supply chain practices such as: S&OP / Integrated Business Planning Supply risk management Inventory optimization Supplier collaboration frameworks Logistics visibility and execution models Establish operational KPIs and governance to improve predictability, responsiveness, and resilience. Architect the Digital Supply Chain Tra

About the Team The Stargate team is responsible for building the physical infrastructure that powers large-scale AI systems. We design and deliver next-generation data centers optimized for dense compute clusters, advanced networking, and rapidly evolving hardware platforms. This work sits at the intersection of hardware engineering, systems architecture, and infrastructure execution—translating cutting-edge compute roadmaps into scalable, production-ready environments. Our teams partner across silicon vendors, server and storage OEMs, networking teams, and data center engineering organizations to bring new capacity online quickly, reliably, and at global scale. About the Role We are seeking a CPU & Storage Technical Lead to define and drive the server compute and storage architecture strategy for Stargate infrastructure. In this role, you will own technical direction across CPU platforms, memory configurations, local and disaggregated storage systems, and their integration into large-scale AI clusters. You will evaluate vendor roadmaps, lead platform tradeoff decisions, and ensure compute and storage systems are optimized for training, inference, and supporting services. You will work cross-functionally with hardware engineering, performance modeling, networking, supply chain, and deployment teams, as well as external partners such as AMD, Intel, OEMs, ODMs, and storage vendors. This is a highly strategic role for someone who can operate deeply at the component level while also driving long-range infrastructure decisions. Key Responsibilities Own CPU and storage technical strategy for Stargate compute infrastructure across current and future generations. Evaluate CPU platforms across performance, efficiency, memory bandwidth, PCIe topology, cost, and roadmap alignment. Define storage architectures for AI environments, including boot media, local NVMe, shared storage, caching tiers, metadata services, and high-performance data pipelines. Drive server platform de

About the Team OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. The Compute team works on the design of our AI supercomputers, doing everything from workload modeling to influencing accelerator design. We’re leaning into our partnerships to make system and data center co-design an integral part of this process, and are looking for engineers to design AI supercomputers solutions for data center applications This team is responsible for working with partners to optimize their hardware for our workloads, identifying promising new deep learning accelerators, and bringing those hardware platforms to production. If you’re excited to work at the intersection of cutting edge deep learning, hardware system, and data center design this role is for you! About the Role We’re looking for a Product Reliability Engineer to own reliability engineering for advanced IT hardware, from printed circuit board assemblies (PCBAs) through compute and networking trays, systems, and fully integrated racks. You’ll translate operating conditions and service-life goals into reliability requirements, design and execute qualification tests, and drive failure analysis and corrective-action verification from development through production and field deployment. Working with electrical, mechanical, thermal, manufacturing, quality, and data center teams, suppliers, and manufacturing partners, you’ll use test and field evidence to improve hardware durability, serviceability, and availability. This role

JLL empowers you to shape a brighter way . Our people at JLL are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people and empowering them to thrive, grow meaningful careers and to find a place where they belong. Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward. Design Coordinator Job Description Position Overview The Design Coordinator supports the design and development process for Data Center project, serving as a key liaison between design teams, clients, project managers, and other stakeholders. This role ensures design projects are executed efficiently, on schedule, and in alignment with client requirements and brand standards. Key Responsibilities Project Coordination & Management The Design Coordinator manages design project timelines, tracks deliverables, and ensures all stakeholders remain informed of project status. They coordinate meetings, prepare agendas, document action items, and follow up on outstanding tasks to maintain project momentum. Design Support & Documentation This role involves organizing and maintaining design files, specifications, drawings, and project documentation. The coordinator ensures all design materials are current, properly archived, and accessible to relevant team members

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to seek, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. What you’ll be doing: Working closely with product design engineers, you'll perform PCB layout of high speed/high-density value-conscious PCBs for all business units at NVIDIA (GPU Desktop, Notebook, Automotive, Professional, Data Center, Deep Learning, and AI), all using Cadence PCB design tools. Focus will be on the complete development of CAD layout from symbol creation, floor planning, and detailed component placement, constraints management, with a concept of topology and signal/trace integrity. You will be responsible for the design releases required generation of artwork files, ODB++, and electronic PCB documentation. Your designs will need to follow SI constraints, EMI/RFI control and FCC, UL and European regulations, IPC specifications and NRC regulations. What we need to see: B.Sc. in Electronic Engineer degree or equivalent experience. 5+ years of experience in high-speed design. Having a detailed knowledge of circuit design and consideration for layout, routing, and timing constraints, DFM, DFA, DFT constraints in volume manufacturing is needed for this role. Be an authority in using Cadence Allegro PCB design tools. Have a deep understanding of High-Density Interconnect PCB layout and PCB Signal Integrity. Knowledge in PCB ma

We are looking to hire a senior CPU Compiler performance Engineer for an exciting and fun role at NVIDIA. We craft outstanding compilers that realise the potential of NVIDIA's CPUs designed for the world's largest AI and computing markets: https://www.nvidia.com/en-in/data-center/grace-cpu/ . Our compiler organisation makes its mark on every CPU, GPU and compute unit that NVIDIA builds. Would you like to be part of this outstanding organisation? We need you to design compiler and hardware software together including developing new technologies to help with hardware software co-design. These compilers are key for the performance of AI, HPC and other performance critical software deployed on NVIDIA Data Centres, on the cloud and at super computing centres around the world. In this role you will solve critical problems working alongside an outstanding engineering team with vision in Compiler technology and systems software, doing what you enjoy! You will also be collaborating with the relevant upstream projects and improving the state of the art If this sounds like a fun challenge, we would be delighted to hear from you!! What you will be doing: Work with a geographically distributed partner organisation to understand, modify and improve CPU Compiler SW at NVIDIA. Analyse AI workloads to champion improvements in both new hardware and compiler toolchain and improve hardware-software co-design. Contribute new features and optimisation techniques targeting NVIDIA CPUs engaging with upstream and open source communities. Develop compiler SW that is optimised for performance. Be part of a team that is at the centre of artificial intelligence, high-performance computing and data centre technologies. Contribute towards the development of next generation compute </

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that power artificial intelligence (AI), high-performance computing, graphics, and data-center applications. Our engineers collaborate across global teams to deliver next-generation memory architectures, advanced design methodologies, and innovative semiconductor solutions. As an HBM Design Engineer Intern, you will work alongside experienced memory engineers on the design, development, and validation of advanced HBM products. This role provides hands-on experience with digital design, circuit design, design verification, simulation, and semiconductor development flows while collaborating with Design, Verification, Physical Design, Product Engineering, and CAD teams. Responsibilities Assist with the design, simulation, analysis, and verification of HBM memory and logic circuits using industry-standard EDA tools. Support RTL development, circuit implementation, timing analysis, power analysis, and functional verification activities. Develop scripting, automation, and AI-assisted workflows to improve design productivity, debug efficiency, and design-flow quality. Participate in design reviews, technical discussions, and debugging activities, leveraging AI-enabled analysis to accelerate root-cause identification and engineering decision-making. Document technical work, experimental results, build methodologies, and AI-assisted insigh

Job Details: Job Description: The Role and Impact As a GPU Logic Design Engineer, you will contribute to the design and validation of cutting-edge graphics IPs, including compute, display, and media units. You will be immersed in the creation of register transfer level (RTL) coding, simulation, and optimization strategies to meet power, performance, area, and timing goals. By leveraging your expertise, you will play a pivotal role in enabling high-quality integration of GPU blocks into larger system-on-chip (SoC) designs, directly impacting Intel's future graphics technologies. Business Group You will be joining Intel's Data Center Group (DCG), a team dedicated to driving innovation and delivering high-performance solutions for data-centric workloads. The group focuses on developing advanced graphics hardware that powers data center GPU solutions, supporting Intel's broader mission of creating world-changing technology that enriches lives. It offers an exciting environment where collaboration and technical excellence intersect to shape the future of visual computing. Key Responsibilities - Develop logic design, RTL coding, and simulation for graphics IPs, ensuring compliance with power, performance, area, and timing requirements. - Participate in defining architecture and microarchitecture features for GPU blocks. - Optimize logic design to support physical implementation while maintaining design integrity. - Review and implement verification plans to ensure design features are accurately tested across verification hierarchies. - Drive unit-level verification and resolve RTL test failures to ensure feature correctness. - Support SoC customers in integrating GPU blocks effectively for high-quality results. <p style="text-align:inhe

Job Details: Job Description: The Role and Impact As a Circuit Design Engineer, you will play a pivotal role in designing and optimizing cutting-edge digital circuits for custom blocks such as SRAM, register files, memory compilers, and caches. In this role, you'll focus on schematic entry, simulation, and functionality verification, ensuring designs meet power, performance, and area goals. Your contributions will directly impact the development of high-performance solutions used across Intel's data center technologies. Business group You will be part of the Data Center Group (DCG), a team dedicated to delivering innovative technology solutions that power the world's data centers and transform how businesses operate. By enabling advanced computing capabilities, the DCG team plays a critical role in supporting Intel's commitment to shaping the future of computing. What You’ll Do Key responsibilities will include but not limited to: Design and optimize digital circuits for custom blocks, including SRAM, register files, memory compilers, and caches. Perform circuit design, schematic entry, simulation, and functionality verification for major blocks. Create block-level DFT models, develop memory test tools, and enhance design flows/methodologies for improved efficiency. Collaborate with architecture, layout, and cross-functional teams to ensure optimal circuit performance, power, area, and yield. Analyze and resolve circuit design issues, driving innovations to reduce leakage, optimize performance, and enhance robustness of circuits. Characterize memory instances and memory compilers to ensure high-quality designs that meet specified design goals. Behavioral traits that we are looking for: <

Job Details: Job Description: This position requires candidates to upload a resume in English; you are welcome to upload multiple versions of your resume if you prefer but an English version of your resume will be required to be considered for this position. We are looking for someone who is passionate about working hands-on with both internal and external teams to deliver impactful Fleet and Scale software solutions that are critical to Data Center customers. You will be part of a team responsible for developing Customer Fleet and Scale capabilities that enable high-quality Intel server product launches and improve in-fleet customer experience. The ideal candidate is a quick learner, results-oriented, and comfortable operating in a dynamic environment. As a Cloud Software Development Engineer with uArch expertise, you will play a key role in developing customer fleet health software capabilities and ecosystem. The position focuses on the development, validation, maintenance, and debugging of cloud-scale platform monitoring, telemetry, diagnostics, and fleet screening software used by Intel and hyperscale cloud customers to improve Xeon platform quality, reliability, and deployment readiness. You will work closely with architecture, platform validation, manufacturing, and customer engineering teams throughout the server product lifecycle. The role involves developing customer-consumable software that provides visibility into system state, platform telemetry, hardware health indicators, and Intel Architecture internals to help customers solve in-field and at-scale operational challenges. Responsibilities Develop and maintain screening software capabilities supporting customer fleet health and platform quality initiatives. Design, develop, and optimize telemetry collection, diagnostics,

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Job Description At Micron, we are transforming how the world uses information to enrich life. The High Bandwidth Memory (HBM) Design team develops industry-leading memory solutions that power Artificial Intelligence (AI), high-performance computing, graphics, and data center applications. Our team collaborates across Design, Verification, Physical Design, Product Engineering, and CAD organizations to deliver next-generation memory technologies. As an HBM Design Engineer Intern, you will work alongside experienced engineers on the design, development, and validation of advanced HBM products. This internship provides hands-on experience with semiconductor design methodologies, industry-standard EDA tools, and AI-assisted engineering workflows while contributing to real-world memory design projects in a collaborative global environment. Responsibilities Assist with HBM memory and logic design activities, including RTL development, circuit implementation, simulation, verification, and functional analysis. Deve

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Make the choice to join us today. NVIDIA’s DFX team is looking for an exceptional DFT Engineer to help shape the future of compute. As stewards of the entire Scan Test Lifecycle, we drive innovation for the most advanced silicon in the world—spanning 2.5D/3D AI data center platforms, Gaming and Enterprise GPUs, and complex SOCs powering Autonomous Machines, Robotics, and Industrial systems. You will innovate at scale, designing and prototyping breakthrough Test Architectures for reticle sized, multi-chiplet products—from RTL to verification to post-silicon ATE bring-up. Join a globally recognized team that consistently delivers breakthrough performance across multiple high-impact tape-outs each year. What you'll be doing: Develop and deploy Industry-leading test methodologies on NVIDIA’s next-generation silicon platforms. Collaborate with leading EDA vendors to shape tool capabilities that meet NVIDIA’s ambitious design goals, and partner with internal CAD teams to drive scalable, automated solutions. Co-architect novel DFT strategies alongside VLSI and Product Engineering teams to push the boundaries of silicon test innovation. Own the full ATPG lifecycle—verification, coverage analysis, pattern generation, and ATE bring-up—across NVIDIA’s full product portfolio. Guide and mentor junior engineers, helping them navigate complex design

NVIDIA’s invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern deep learning — the next era of computing — with the GPU acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. Today, we are increasingly known as “the AI computing company.” We're looking to grow our company and establish teams with the most thoughtful people in the world. We are looking for an excellent engineering manager to own and deliver an end to end manageability stack for Data Center Systems. We are seeking an experienced manager who is deeply technical, hands-on, and has a wide system view. You will manage a team of experts, design & build OpenBMC based manageability software stack for NVIDIA’s next generation Data Center Compute Systems. We want to grow our teams with the smartest people in the world. If you're creative and autonomous, we want to hear from you! What you’ll be doing: Own and deliver OpenBMC based manageability stack for next generation Data Center Compute Systems. Own firmware delivered to data centers in terms of quality, reliability and telemetry performance. Manage and lead a distributed team of software engineers to deliver firmware stack with high quality. Work with data center architects and cloud customers for correct requirements and scope implementation to ensure speed of light product development. Work closely with cross functional teams to ensure scalable manageability architecture for all data centers products Drive efficiency, reliability and optimization in firmware architecture from a data center view point. Work closely with customers and internal teams to resolve issues at Speed of Light. What we need to see: BS, MS, or PhD in EE/CS or related field o

About Anthropic Anthropic’s mission is to create reliable, interpretable, and steerable AI systems. We want AI to be safe and beneficial for our users and for society as a whole. Our team is a quickly growing group of committed researchers, engineers, policy experts, and business leaders working together to build beneficial AI systems. About the role Anthropic's Business Risk & Insurance (BRI) team, part of Treasury, safeguards the company's balance sheet, people and physical assets. We are the financial and operational safety net for a company building some of the world's most advanced AI systems, from large-scale compute and data center infrastructure to our offices and the products we put in customers' hands. The team is scaling quickly as Anthropic grows. As a Risk & Insurance Specialist, you'll build operational excellence across contracts, claims, and day-to-day insurance operations, using AI and automation to streamline processes wherever you can. You'll work closely with Compute, Engineering, Finance, Legal, Security, Product and Payroll to spot emerging risks early, help structure global insurance programs, support our risk-financing strategy and drive loss prevention. This is a rare chance to insure one of the fastest-growing companies, where parts of the risk landscape are still being defined, and to help Anthropic pursue its mission boldly by keeping our operations resilient and protected. Key responsibilities Insurance review of contracts: Review insurance and indemnity requirements in customer, vendor, lease, and compute agreements, and advise Legal and business partners on compliant, practical positions. Insurance operations: Manage claims intake and tracking, certificates of insurance, broker coordination, and policy administration. Build a data warehouse / repository and repeatable processes as volume scales. Data gathering and reporting: Collect and maintain exposure data (property values, payroll, revenue, headcount, etc.) for renewals, au