Design Layout Engineer Jobs

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products. Design, implementation and integration of synchronous and asynchronous custom digital block Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits. Parasitic modeling and design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Mentor and lead young designers. Usage & working with AI Skills is must Strong

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities will include, but are not limited to: Design, implementation and integration of complex analog circuits such as CMOS Amplifiers, Comparators, Bandgap References, LDOs, Charge Pumps, Oscillators, DLL, IO Buffers, Analog Test Mux, Process Monitor, and Temperature sensors for advanced DRAM products. Design, implementation and integration of synchronous and asynchronous custom digital block Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Analog/Memory/Logic circuits. Parasitic modeling and design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing Performing verification processes with modeling and simulation using industry standard simulators Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Mentor and lead young designers. Strong AI proficiency, a solid understanding of agentic AI model

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Principal Design Engineer in Micron’s NVEG (Non‑Volatile Engineering Group) organization will own and evolve the timing-critical circuitry between the NAND array and page buffer. This role is for a designer who is equally strong in architecture, transistor-level implementation, and physical aware timing closure – and who can lead technical direction across teams to deliver robust, scalable datapath solutions. You will drive designs that directly impact throughput, timing margin, power and yield, partnering closely with page buffer, array device, clocking, physical design, test, and product teams. Responsibilities Own internal NAND datapath circuits including array redundancy circuits, wave pipeline / pulse based datapath arctitechture and data line sensing circuits. Define scalable datapath architecture supporting multi-plane and high-parallelism operation. Define and analyse clock/data timing schemes for long interconnects and large-array topologies. Lead timing adjustment and skew management strategy. Drive layout-aware circuit design with attention to: matching/symmetry for sensing paths, shielding/guarding for sensitive nodes. Parasitic-aware sizing and RC-driven timing closure. Array pitch constraints, blockages and repeatable layout templates. Partner tightly with layout to review critical routes and implement practical fixes. Perform SPICE/Fast-SPICE simulations across PVT, aging and variability via Monte Carlo. Define characterization structures and debug

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays. Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation. To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website. About the Role We're looking for an experienced Principal Hardware Design Engineer/Manager to lead PCB design and development for next-generation, high-performance cellular base stations. You'll architect the board-level circuitry that complements our custom silicon — spanning digital processing, high-speed SerDes, power management, and RF transmission/reception — to deliver a solution that's both high-reliability and low-cost/power. This opportunity is a high-visibility technical leadership role based in San Diego, CA: you'll own PCB system architecture from concept through qualification, working shoulder-to-shoulder with various domain experts to ensure everything comes together. What You'll Do Own PCB development end-to-end, from concept through production Design and implement RF, analog, digital, and power circuits for high-performance base station products Partner with experts on floor planning and PCB constraints for seamless integration Lead and review schematic capture and PCB layout Optimize PCB stack-up for per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we build the memory and storage that powers everything from massive data centers to the devices people rely on every day. Our design teams carry silicon all the way to systems—developing advanced memory architectures, shaping the products around them, and validating the solutions used across the globe. We take real ownership of the technology we create, and we're always pushing what memory can do! As a Staff Analog Design Engineer, you'll design and analyze the analog and digital circuits at the core of our memory products, directly shaping their performance, cost, and reliability. You'll work alongside Micron's design and verification teams around the world and support Product Engineering, Test, Probe, Process Integration, Assembly, and Marketing to build products that optimize manufacturing and keep customers coming back. It's a role where your circuit decisions show up in silicon that ships at scale. Responsibilities: Design, optimize, and verify block-level analog and mixed-signal circuits for DRAM Evaluate new circuit topologies to improve block PPAC Expand verification coverage to strengthen robustness and mass-production yield Partner with global design groups, guide layout through post-layout simulation, and support silicon-to-simulation correlation Apply agentic AI and automation tools to improve design quality and efficiency Minimum Qualifications: Bachelor's degree in Electrical Engineering with 6+ years of semicond

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. At Micron, we build the memory and storage that powers everything from massive data centers to the devices people carry every day. Our DRAM IP Design team shapes the circuits at the heart of these products, carrying innovative designs from concept all the way to silicon. We work across global design, verification, and product teams, and the work we do here helps define where the semiconductor industry goes next! As a Principal Analog Design Engineer, you'll help shape the next generation of Micron's memory products, bringing circuit designs to life and directly influencing their performance, quality, and reliability. You'll partner with design, verification, and product teams around the world, operating with the independence and technical depth expected of a principal engineer. It's a role where your circuit decisions show up in silicon that ships at scale. Responsibilities: Design, optimize, and verify block-level analog and mixed-signal circuits for DRAM Propose, evaluate, and implement new or improved circuit topologies to enhance block PPAC Work with the internal data science team and EDA vendors to leverage agentic AI and AI-assisted design flows for circuit optimization Expand verification coverage to strengthen robustness and mass-production yield Partner with global design groups, guide layout through post-layout simulation, support silicon-to-simulation correlation, and operate independently to define solutions and methods Minimum Qualifications:

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. For more than 45 years, Micron Technology, Inc. has redefined innovation with the world’s most advanced memory and semiconductor technologies. We’re an international team of visionaries and scientists, developing groundbreaking technologies that are transforming how the world uses information to enrich life. As a Principal Engineer, you will be an integral part of our HIG HBM Team in Hyderabad, India, responsible for designing and developing complex Application-Specific Integrated Circuits to meet our product's specifications and requirements for High Bandwidth Memories, working for intensive applications such as artificial intelligence and high performance computing solution. Your expertise will contribute to the successful realization of pioneering semiconductor products, enabling our company to maintain its competitive edge in the industry. Role and Responsibilities Must have a solid understanding of die design . This includes knowledge of various die components, their functions, and how they interact within the overall tool. Familiarity with the principles of die design is essential to create effective and efficient layouts. Industry Involvement : You actively participate in standards committees, representing Micron and staying informed about industry developments. Leading Project Layout Team : You lead the establishment and growth of a layout team to meet Micron’s global HBM layout requirements. Technical Expertise :

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. Responsibilities Design and maintain standard cells for new DRAM products on new technology Closely collaborate with DTCO team to develop stdcells architecture for emerging technologies Characterization and modeling of Standard cells to provide timing/power model Quality Analysis of characterized liberty models in terms of performance, Power and Functionality Develop automation test bench/flow/tools to improve the work efficiency and help data analysis Co-work with international colleagues on developing new flows and tools for stdcells design Ability to identify stdcells design & char pain points suitable for AI-based automation and collaborate with cross‑functional teams to deploy scalable solutions. Requirements Good understanding of CMOS circuit design Good knowledge of CMOS device physics and layout Experience in total stdcells flow from DTCO development/ spec definition till lib release RTL/GDS flow setup, block level timing analysis, ICC2 experience. Preferred Synopsys EDA flow Finefet & planner experience required. Experience in any characterization tools (Siliconsmart/Liberate)and Cadence Virtuoso preferred. Experience in Primetime, Solido Analytics Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, Simvision Experience in Standard Cell design, layout and verification Experience in Skill, TCL, Per

Our vision is to transform how the world uses information to enrich life for all. Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing. Define physical design rules for current and future Non-Volatile Memory (NVM) technologies from conception to full production ramp. Interact with process integration team to keep all technology developments up to date, to ensure DR's are accurate. Interact with design teams to evaluate the feasibility of different layout and architecture options (i.e., design rule and process limitations). Interact across multi-disciplinary teams to understand product and test structure failures and their interaction with layout and mask generated data Support design rule checking (DRC) of both base and mask layers and interface with physical verification team. Define algorithms for generation of mask data from drawn base layer data. Involve projects across multi-disciplinary teams focusing on layout and mask generation issues About Micron Technology, Inc. We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of hig

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. A CAD Engineer is a development/support role focusing on semi-conductor / EDA design flows/tools. At Micron Technology, Inc., you will be working in a fast-paced, collaborative, production support role evaluating, developing, improving, and debugging both in-house and commercial EDA tools and flows for the design, physical layout, and verification of CMOS integrated circuits. Responsibilities and Tasks include, but not limited to: Serves as a subject matter of expert within a technical discipline Defines and leads large projects Provide input to team members and managers on technical or innovation Guide the ML/AI implementation on CAD flows Providing training, documentation, and support to end-users on new tools and methods Collaborating closely with design and process teams Develop and apply CAD software engineering methods, theories, and research techniques in support of the organization's product development. Assignments include crafting and developing CAD software, assessing architecture and hardware limitations, and defining and implementing CAD software engineering applications. Successful candidates will have the following: Coursework or experience in EE, CE or CS including VLSI circuit design and software Expertise in IC design CAD tools (schematics, layouts, simulation, and verification tools) is required Exposure to CMOS circuit design and implementation including area, speed, and power tradeoffs Excellent programming fundamentals are required In-d

Job Details: Job Description: Position Overview As a Platform Hardware Design Engineer, you will provide technical leadership for the architecture, design, integration, bring-up, and validation of complex platform hardware. You will drive hardware development end-to-end, translating high level system requirements into detailed circuit and component specifications and leading designs from architecture and schematic development through PCB implementation, board power-on, debugging, validation, and delivery. You will be expected to make platform level technical decisions, resolve complex and ambiguous multidisciplinary problems, lead critical design reviews, drive cross-functional alignment, mentor engineers, and influence hardware development practices across projects. Our Business Group You will be joining the Silicon and Platform Engineering Group (SPE), an organization at Intel committed to advancing Intel's mission of delivering world-class silicon and platform solutions. The group focuses on developing integrated systems that align with customer needs and support Intel's broader goals of leadership in technology innovation. SPE collaborates across diverse domains to ensure Intel platforms meet performance, reliability, and scalability requirements. Our work sits at the intersection of silicon, board hardware, firmware, validation, signal and power integrity, mechanical and thermal engineering, PCB technology, manufacturing, and system integration. Our senior hardware engineers have a broader responsibility than executing an individual design. They help establish platform architecture, guide implementation, identify and qualify appropriate hardware solutions, provide technical leadership during board power-on and debug, and lead resolution of schematic, layout, SI/PI, and hardware issues. Key Responsibilities Platform Architecture and End-to-End Technical Ownership

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. Our team builds AI-driven software systems for Circuit Design: combining automation algorithms, DL models and agentic workflows to accelerate end-to-end design automation. Come join this integral team in our Circuit Solutions Group! What you'll be doing: Work within a multi-functional team on various projects involving Pre-silicon and Post Silicon custom circuit design and related data, Circuit/Layout Optimization and Spice correlation Research and implement techniques on frontier solutions of electronic design automation. Build and innovate agentic AI solution for VLSI design problem. Responsible for analyzing the problem or datasets, raise and validate hypotheses, design and build models and algorithm until they reach the desired QOR. What we need to see: MS (or equivalent experience) with 3+ years’ experience or PhD with 1+ years’ experience in Electrical/Computer Engineering degree Experience in the following fields is a strict requirement for this role: Combinatorial Optimization, Agentic AI and large language models, Machine Learning for Chip Design & EDA Experience in Algorithms/Data Structures/

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We’re building the next generation of DRAM technology and pushing what’s possible at the intersection of device physics and circuit design. Our team thrives on solving deep technical challenges and turning innovative ideas into high-performance, manufacturable memory solutions. If you’re excited about influencing future technology nodes and working on designs that ship at scale, you’ll feel right at home with us! As a Staff/Principal DRAM Design Engineer, you’ll play a critical role in shaping memory architectures and circuit innovations that directly impact product performance, power, and reliability. This is a hands-on design role where your expertise will drive key decisions from concept through silicon validation, while collaborating with cross-functional teams to deliver meaningful results. Responsibilities: Lead design and optimization of DRAM circuits including memory array, control logic, datapath, and test logic Perform and analyze circuit simulations using tools such as SPICE and Verilog Evaluate architectural trade-offs impacting power, performance, and die size Integrate layout parasitics into simulations and drive design for manufacturability Define validation strategies including test chip development and silicon bring-up Minimum Qualifications: Bachelor’s degree in Electrical Engineering or related field 5+ years of circuit design experience or product engineering experience Strong understanding of analog and digital